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features ? high-performance, low-power 32-bit atmel ? avr ? microcontroller ? compact single-cycle risc instruction set including dsp instructions ? read-modify-write instructions and atomic bit manipulation ? performance ? up to 64dmips running at 50mhz from flash (1 flash wait state) ? up to 36dmips running at 25mhz from flash (0 flash wait state) ? memory protection unit (mpu) ? secure access unit (sau) providing user-defined peripheral protection ? picopower ? technology for ultra-low power consumption ? multi-hierarchy bus system ? high-performance data transfers on separate buses for increased performance ? 12 peripheral dma channels improve speed for peripheral communication ? internal high -speed flash ? 256kbytes and 128kbytes versions ? single-cycle access up to 25mhz ? flashvault technology allows pre-programmed secure library support for end user applications ? prefetch buffer optimizing instru ction execution at maximum speed ? 100,000 write cycles, 15-year data retention capability ? flash security locks and us er-defined configuration area ? internal high-speed sram, si ngle-cycle access at full speed ?32kbytes ? interrupt controller (intc) ? autovectored low-latency interrupt service with programmable priority ? external interrupt controller (eic) ? peripheral event system for direct pe ripheral to periph eral communication ? system functions ? power and clock manager ? sleepwalking power saving control ? internal system rc oscillator (rcsys) ? 32 khz oscillator ? multipurpose oscillator, phase locked loop (pll), and digital frequency locked loop (dfll) ? windowed watchdog timer (wdt) ? asynchronous timer (ast) with real-time clock capability ? counter or calendar mode supported ? frequency meter (freqm) for accurate measuring of clock frequency ? six 16-bit timer/co unter (tc) channels ? external clock inputs, pwm, capture, and various counting capabilities ? pwm channels on all i/o pins (pwma) ? 8-bit pwm with a source clock up to 150mhz ? four universal synchronous/asynchro nous receiver/transmitters (usart) ? independent baudrate generator, support for spi ? support for hardware handshaking ? one master/slave serial peripheral inte rface (spi) with chip select signals ? up to 15 spi slaves can be addressed 32145bs?01/2012 32-bit atmel avr microcontroller at32uc3l0256 at32uc3l0128 summary
2 32145bs?01/2012 at32uc3l0128/256 ? two master and two slave two-wire interfaces (twi), 400kbit/s i 2 c-compatible ? one 8-channel analog-to -digital converter (adc) with up to 12 bits resolution ? internal temperature sensor ? eight analog comparators (ac) with optional window detection ? capacitive touch (cat) module ? hardware-assisted atmel ? avr ? qtouch ? and atmel ? avr ? qmatrix touch acquisition ? supports qtouch and qmatrix capture from capacitive touch sensors ? qtouch library support ? capacitive touch buttons, sliders, and wheels ? qtouch and qmatrix acquisition ? on-chip non-intrusive debug system ? nexus class 2+, runtime control, non-intrusive data and program trace ? awire single-pin programming trace and debug interface muxed with reset pin ? nanotrace provides trace capabilities through jtag or awire interface ? 48-pin tqfp/qfn/tllga (36 gpio pins) ? five high-drive i/o pins ? single 1.62-3.6 v power supply
3 32145bs?01/2012 at32uc3l0128/256 1. description the atmel ? avr ? at32uc3l0128/256 is a complete system-on-chip microcontroller based on the avr32 uc risc processor running at frequencies up to 50mhz. avr32 uc is a high-per- formance 32-bit risc microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance. the processor implements a memory protection unit (mpu) and a fast and flexible interrupt con- troller for supporting m odern and real-tim e operating systems. the se cure access unit (sau) is used together with the mpu to provide the required security and integrity. higher computation capability is achieved using a rich set of dsp instructions. the at32uc3l0128/256 embeds state-of-the-art picopower technology for ultra-low power con- sumption. combined power control techniques are used to bring active current consumption down to 174a/mhz, and leakage down to 220na while still retaining a bank of backup regis- ters. the device allows a wide range of trade-offs between functionality and power consumption, giving the user the ability to reach the lowest possible power consumptio n with the feature set required for the application. the peripheral direct memory access (dma) controller enables data transfers between periph- erals and memories without processor involvement. the peripheral dma controller drastically reduces processing overhead when transferring continuous and large data streams. the at32uc3l0128/256 incorporates on-chip flash and sram memories for secure and fast access. the flashvault technology allows secure libraries to be programmed into the device. the secure libraries can be executed while the cpu is in secure state, but not read by non- secure software in the device. the device can thus be shipped to end customers, who will be able to program their own code into the device to access the secure libraries, but without risk of compromising the proprietary secure code. the external interrupt controller (eic) allows pins to be configured as external interrupts. each external interrupt has its own interrupt request and can be individually masked. the peripheral event system allows peripherals to receive, react to, and send peripheral events without cpu intervention. asynchronous interrupts allow advanced peripheral operation in low power sleep modes. the power manager (pm) improves design flexibility and securi ty. the power ma nager supports sleepwalking functionality, by which a module can be selectively activated based on peripheral events, even in sleep modes where the module clock is stopped. power monitoring is supported by on-chip power-on reset (por), brown-out detector (bod), and supply monitor (sm). the device features several oscillators, such as phase locked loop (pll), digital frequency locked loop (dfll), oscillator 0 (osc0), and syst em rc oscillator (rcsys). either of these oscillators can be used as source for the system clock. the dfll is a programmable internal oscillator from 20 to 150mh z. it can be tuned to a high accura cy if an accurate reference clock is running, e.g. the 32khz crystal oscillator. the watchdog timer (wdt) will reset the device unless it is periodically serviced by the soft- ware. this allows the device to recover from a condition that has caused the system to be unstable. the asynchronous timer (ast) combined with th e 32khz crystal oscillator supports powerful real-time clock capabilities, with a maximum timeou t of up to 136 years. the ast can operate in counter mode or calendar mode.
4 32145bs?01/2012 at32uc3l0128/256 the frequency meter (freqm) allows accurate measuring of a clock frequency by comparing it to a known reference clock. the device includes six identical 16-bit timer/counter (tc) channels. each channel can be inde- pendently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. the pulse width modulation controller (pwma) provides 8-bit pwm channels which can be syn- chronized and controlled from a common timer. one pwm channel is available for each i/o pin on the device, enabling applications that require multiple pwm outputs, such as lcd backlight control. the pwm channels can operate independently , with duty cycles se t individually, or in interlinked mode, with multiple ch annels changed at the same time. the at32uc3l0128/256 also features many communication interfaces, like usart, spi, and twi, for communication intensive applications . the usart supports different communication modes, like spi mode and lin mode. a general purpose 8-channel adc is provided, as well as eight analog comparators (ac). the adc can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering up to 12-bit resolution. the adc also provides an internal temperature sensor input channel. the analog comparators can be paired to detect when the sensing voltage is within or outside the defined reference window. the capacitive touch (cat) module senses touch on external capacitive touch sensors, using the qtouch technology. capacitive touch sensor s use no external mechanical components, unlike normal push buttons, and therefore demand less maintenance in the user application. the cat module allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced. all touch sensors can be configured to oper ate autonomously without software interaction, allowing wakeup from sleep modes when activated. atmel offers the qtouch library for embedding capacitive touch buttons, sliders, and wheels functionality into avr microcontrollers. the patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys as well as adjacent key suppression ? (aks ? ) technology for unambiguous detection of key events. the easy-to-use qtouch suite toolchain allows you to explore, develop, and debug your own touch applications. the at32uc3l0128/256 integrates a class 2+ nexus 2.0 on-chip debug (ocd) system, with non-intrusive real-time trace and full-speed read/write memory access, in addition to basic run- time control. the nanotrace interface enables trace feature for awire- or jtag-based debuggers. the single-pin awire interface allows all features available through the jtag inter- face to be accessed through the reset pin, a llowing the jtag pins to be used for gpio or peripherals.
5 32145bs?01/2012 at32uc3l0128/256 2. overview 2.1 block diagram figure 2-1. block diagram system control interface interrupt controller asynchronous timer peripheral dma controller hsb-pb bridge b hsb-pb bridge a s mm m s s m external interrupt controller high speed bus matrix generalpurpose i/os general purpose i/os pa pb extint[5..1] nmi g c l k [ 4 . . 0 ] pa pb spi dma miso, mosi npcs[3..0] usart0 usart1 usart2 usart3 dma rxd txd clk rts, cts watchdog timer sck jtag interface mcko mdo[5..0] mseo[1..0] evti_n tdo tdi tms configuration registers bus 128/256 kb flash s flash controller evto_n avr32uc cpu nexus class 2+ ocd instr interface data interface memory interface local bus 32 kb sram memory protection unit local bus interface frequency meter pwm controller pwma[35..0] timer/counter 0 timer/counter 1 a[2..0] b [ 2 . . 0 ] twi master 0 twi master 1 dma twi slave 0 twi slave 1 dma 8-channel adc interface dma ad[8..0] advrefp power manager reset controller sleep controller clock controller xin32 xout32 osc32k rcsys x i n 0 x o u t 0 osc0 dfll tck awire reset_n capacitive touch module dma csb[16:0] smp csa[16:0] sync ac interface acrefn acan[3..0] acbn[3..0] acbp[3..0] acap[3..0] twck twd twalm twck twd twalm rc32k rc120m glue logic controller in[7..0] out[1:0] dataout sau s/m vdiven dis trigger adp[1..0] rc32out pll g c l k _ i n [ 1 . . 0 ] clk[2..0]
6 32145bs?01/2012 at32uc3l0128/256 2.2 configuration summary table 2-1. configuration summary feature at32uc3l0256 at32uc3l0128 flash 256kb 128kb sram 32kb gpio 36 high-drive pins 5 external interrupts 6 twi 2 usart 4 peripheral dma channels 12 peripheral event system 1 spi 1 asynchronous timers 1 timer/counter channels 6 pwm channels 36 frequency meter 1 watchdog timer 1 power manager 1 secure access unit 1 glue logic controller 1 oscillators digital frequency locked loop 20-150 mhz (dfll) phase locked loop 40-240 mhz (pll) crystal oscillator 0.45-16 mhz (osc0) crystal oscillator 32 khz (osc32k) rc oscillator 120mhz (rc120m) rc oscillator 115 khz (rcsys) rc oscillator 32 khz (rc32k) adc 8-channel 12-bit temperature sensor 1 analog comparators 8 capacitive touch module 1 jtag 1 awire 1 max frequency 50 mhz packages tqfp48/qfn48/tllga48
7 32145bs?01/2012 at32uc3l0128/256 3. package and pinout 3.1 package the device pins are multiplexed with pe ripheral functions as described in section 3.2.1 . figure 3-1. tqfp48/qfn48 pinout gnd 1 pa09 2 pa08 3 pa03 4 pb12 5 pb00 6 pb02 7 pb03 8 pa22 9 pa06 10 pa00 11 pa05 12 pa02 13 pa01 14 pa07 15 pb01 16 vddin 17 vddcore 18 gnd 19 pb05 20 pb04 21 reset_n 22 pb10 23 pa21 24 pa14 36 vddana 35 advrefp 34 gndana 33 pb08 32 pb07 31 pb06 30 pb09 29 pa04 28 pa11 27 pa13 26 pa20 25 pa15 37 pa16 38 pa17 39 pa19 40 pa18 41 vddio 42 gnd 43 pb11 44 gnd 45 pa10 46 pa12 47 vddio 48
8 32145bs?01/2012 at32uc3l0128/256 figure 3-2. tllga48 pinout 3.2 peripheral multiplexing on i/o lines 3.2.1 multiplexed signals each gpio line can be assigned to one of the peripheral functions. the following table describes the peripheral signals multiplexed to the gpio lines. gnd 1 pa09 2 pa08 3 pa03 4 pb12 5 pb00 6 pb02 7 pb03 8 pa22 9 pa06 10 pa00 11 pa05 12 pa02 13 pa01 14 pa07 15 pb01 16 vddin 17 vddcore 18 gnd 19 pb05 20 pb04 21 reset_n 22 pb10 23 pa21 24 pa14 36 vddana 35 advrefp 34 gndana 33 pb08 32 pb07 31 pb06 30 pb09 29 pa04 28 pa11 27 pa13 26 pa20 25 pa15 37 pa16 38 pa17 39 pa19 40 pa18 41 vddio 42 gnd 43 pb11 44 gnd 45 pa10 46 pa12 47 vddio 48 table 3-1. gpio controller func tion multiplexing 48- pin pin g p i o supply pin type gpio function ab c d e f gh 11 pa00 0 vddio normal i/o u s a r t 0 txd u s a r t 1 rts s p i npcs[2] p w m a pwma[0] s c i f gclk[0] c a t csa[2] 14 pa01 1 vddio normal i/o u s a r t 0 rxd u s a r t 1 cts s p i npcs[3] u s a r t 1 clk p w m a pwma[1] a c i f b acap[0] t w i m s 0 twalm c a t csa[1]
9 32145bs?01/2012 at32uc3l0128/256 13 pa02 2 vddio high- drive i/o u s a r t 0 rts a d c i f b trigger u s a r t 2 txd t c 0 a0 p w m a pwma[2] a c i f b acbp[0] u s a r t 0 clk c a t csa[3] 4 pa03 3 vddio normal i/o u s a r t 0 cts s p i npcs[1] u s a r t 2 txd t c 0 b0 p w m a pwma[3] a c i f b acbn[3] u s a r t 0 clk c a t csb[3] 28 pa04 4 vddio normal i/o s p i miso t w i m s 0 twck u s a r t 1 rxd t c 0 b1 p w m a pwma[4] a c i f b acbp[1] c a t csa[7] 12 pa05 5 vddio normal i/o (twi) s p i mosi t w i m s 1 twck u s a r t 1 txd t c 0 a1 p w m a pwma[5] a c i f b acbn[0] t w i m s 0 twd c a t csb[7] 10 pa06 6 vddio high- drive i/o, 5v tolerant s p i sck u s a r t 2 txd u s a r t 1 clk t c 0 b0 p w m a pwma[6] e ic extint[2] s c i f gclk[1] c a t csb[1] 15 pa07 7 vddio normal i/o (twi) s p i npcs[0] u s a r t 2 rxd t w i m s 1 twalm t w i m s 0 twck p w m a pwma[7] a c i f b acan[0] e i c nmi (extint[0]) c a t csb[2] 3 pa08 8 vddio high- drive i/o u s a r t 1 txd s p i npcs[2] t c 0 a2 a d c i f b adp[0] p w m a pwma[8] c a t csa[4] 2 pa09 9 vddio high- drive i/o u s a r t 1 rxd s p i npcs[3] t c 0 b2 a d c i f b adp[1] p w m a pwma[9] s c i f gclk[2] e i c extint[1] c a t csb[4] 46 pa10 10 vddio normal i/o t w i m s 0 twd t c 0 a0 p w m a pwma[10] a c i f b acap[1] s c i f gclk[2] c a t csa[5] 27 pa11 11 vddin normal i/o p w m a pwma[11] 47 pa12 12 vddio normal i/o u s a r t 2 clk t c 0 clk1 c at smp p w m a pwma[12] a c i f b acan[1] s c i f gclk[3] c a t csb[5] 26 pa13 13 vddin normal i/o g l o c out[0] g l o c in[7] t c 0 a0 s c i f gclk[2] p w m a pwma[13] c at smp e i c extint[2] c a t csa[0] 36 pa14 14 vddio normal i/o a d c i f b ad[0] t c 0 clk2 u s a r t 2 rts c at smp p w m a pwma[14] s c i f gclk[4] c a t csa[6] 37 pa15 15 vddio normal i/o a d c i f b ad[1] t c 0 clk1 g l o c in[6] p w m a pwma[15] c at sync e i c extint[3] c a t csb[6] 38 pa16 16 vddio normal i/o a d c i f b ad[2] t c 0 clk0 g l o c in[5] p w m a pwma[16] a c i f b acrefn e i c extint[4] c a t csa[8] 39 pa17 17 vddio normal i/o (twi) t c 0 a1 u s a r t 2 cts t w i m s 1 twd p w m a pwma[17] c at smp c at dis c a t csb[8] 41 pa18 18 vddio normal i/o a d c i f b ad[4] t c 0 b1 g l o c in[4] p w m a pwma[18] c at sync e i c extint[5] c a t csb[0] 40 pa19 19 vddio normal i/o a d c i f b ad[5] t c 0 a2 t w i m s 1 twalm p w m a pwma[19] s c i f gclk_in[0] c at sync c a t csa[10] 25 pa20 20 vddin normal i/o u s a r t 2 txd t c 0 a1 g l o c in[3] p w m a pwma[20] s c i f rc32out c a t csa[12] 24 pa21 21 vddin normal i/o (twi, 5v tolerant, smbus) u s a r t 2 rxd t w i m s 0 twd t c 0 b1 a d c i f b trigger p w m a pwma[21] p w m a pwmaod[21] s c i f gclk[0] c a t smp 9 pa22 22 vddio normal i/o u s a r t 0 cts u s a r t 2 clk t c 0 b2 c at smp p w m a pwma[22] a c i f b acbn[2] c a t csb[10] 6 pb00 32 vddio normal i/o u s a r t 3 txd a d c i f b adp[0] s p i npcs[0] t c 0 a1 p w m a pwma[23] a c i f b acap[2] t c 1 a0 c a t csa[9] 16 pb01 33 vddio high- drive i/o u s a r t 3 rxd a d c i f b adp[1] s p i sck t c 0 b1 p w m a pwma[24] t c 1 a1 c a t csb[9] 7 pb02 34 vddio normal i/o u s a r t 3 rts u s a r t 3 clk s p i miso t c 0 a2 p w m a pwma[25] a c i f b acan[2] s c i f gclk[1] c a t csb[11] table 3-1. gpio controller func tion multiplexing
10 32145bs?01/2012 at32uc3l0128/256 see section 3.3 for a description of the various peripheral signals. refer to ?electrical characteristics? on page 41 for a description of the electrical properties of the pin types used. 3.2.2 twi, 5v tolerant, and smbus pins some normal i/o pins offer twi, 5v tolerance, and smbus features. these features are only available when either of the twi functions or the pwmaod function in the pwma are selected for these pins. refer to the ?twi pin characteristics(1)? on page 48 for a description of the electrical properties of the twi, 5v tolerance, and smbus pins. 8 pb03 35 vddio normal i/o u s a r t 3 cts u s a r t 3 clk s p i mosi t c 0 b2 p w m a pwma[26] a c i f b acbp[2] t c 1 a2 c a t csa[11] 21 pb04 36 vddin normal i/o (twi, 5v tolerant, smbus) t c 1 a0 u s a r t 1 rts u s a r t 1 clk t w i m s 0 twalm p w m a pwma[27] p w m a pwmaod[27] t w i m s 1 twck c a t csa[14] 20 pb05 37 vddin normal i/o (twi, 5v tolerant, smbus) t c 1 b0 u s a r t 1 cts u s a r t 1 clk t w i m s 0 twck p w m a pwma[28] p w m a pwmaod[28] s c i f gclk[3] c a t csb[14] 30 pb06 38 vddio normal i/o t c 1 a1 u s a r t 3 txd a d c i f b ad[6] g l o c in[2] p w m a pwma[29] a c i f b acan[3] e i c nmi (extint[0]) c a t csb[13] 31 pb07 39 vddio normal i/o t c 1 b1 u s a r t 3 rxd a d c i f b ad[7] g l o c in[1] p w m a pwma[30] a c i f b acap[3] e i c extint[1] c a t csa[13] 32 pb08 40 vddio normal i/o t c 1 a2 u s a r t 3 rts a d c i f b ad[8] g l o c in[0] p w m a pwma[31] c at sync e i c extint[2] c a t csb[12] 29 pb09 41 vddio normal i/o t c 1 b2 u s a r t 3 cts u s a r t 3 clk p w m a pwma[32] a c i f b acbn[1] e i c extint[3] c a t csb[15] 23 pb10 42 vddin normal i/o t c 1 clk0 u s a r t 1 txd u s a r t 3 clk g l o c out[1] p w m a pwma[33] s c i f gclk_in[1] e i c extint[4] c a t csb[16] 44 pb11 43 vddio normal i/o t c 1 clk1 u s a r t 1 rxd a d c i f b trigger p w m a pwma[34] c at vdiven e i c extint[5] c a t csa[16] 5 pb12 44 vddio normal i/o t c 1 clk2 t w i m s 1 twalm c at sync p w m a pwma[35] a c i f b acbp[3] s c i f gclk[4] c a t csa[15] table 3-1. gpio controller func tion multiplexing
11 32145bs?01/2012 at32uc3l0128/256 3.2.3 peripheral functions each gpio line can be assigned to one of several peripheral functions. the following table describes how the various peripheral functions are selected. the last listed function has priority in case multiple functions are enabled on the same pin. 3.2.4 jtag port connections if the jtag is enabled, the jtag will take control over a number of pins, irrespectively of the i/o controller configuration. 3.2.5 nexus ocd aux port connections if the ocd trace system is enabled, the trace system will take control over a number of pins, irre- spectively of the i/o controller configurat ion. two different ocd trace pin mappings are possible, depending on the configuration of the ocd axs register. for details, see the avr32 uc technical reference manual . table 3-2. peripheral functions function description gpio controller function multiplexing gpio and gpio peripheral selection a to h nexus ocd aux port connections ocd trace system awire dataout awire output in two-pin mode jtag port connections jtag debug port oscillators osc0, osc32 table 3-3. jtag pinout 48-pin pin name jtag pin 11 pa00 tck 14 pa01 tms 13 pa02 tdo 4pa03tdi table 3-4. nexus ocd aux po rt connections pin axs=1 axs=0 evti_n pa05 pb08 mdo[5] pa10 pb00 mdo[4] pa18 pb04 mdo[3] pa17 pb05 mdo[2] pa16 pb03 mdo[1] pa15 pb02 mdo[0] pa14 pb09
12 32145bs?01/2012 at32uc3l0128/256 3.2.6 oscillator pinout the oscillators are not mapped to the normal gp io functions and their muxings are controlled by registers in the system control interface (scif). please refer to the scif chapter for more information about this. 3.2.7 other functions the functions listed in table 3-6 are not mapped to the normal gpio functions. the awire data pin will only be active after the awire is e nabled. the awire dataout pin will only be active after the awire is enabled an d the 2_pin_mode command has been sent. the wake_n pin is always enabled. please refer to section 6.1.4 on page 40 for constraints on the wake_n pin. evto_n pa04 pa04 mcko pa06 pb01 mseo[1] pa07 pb11 mseo[0] pa11 pb12 table 3-4. nexus ocd aux po rt connections pin axs=1 axs=0 table 3-5. oscillator pinout 48-pin pin name oscillator pin 3pa08xin0 46 pa10 xin32 26 pa13 xin32_2 2pa09xout0 47 pa12 xout32 25 pa20 xout32_2 table 3-6. other functions 48-pin pin function 27 pa11 wake_n 22 reset_n awire data 11 pa00 awire dataout
13 32145bs?01/2012 at32uc3l0128/256 3.3 signal descriptions the following table gives details on signal names classified by peripheral. table 3-7. signal descriptions list signal name function type active level comments analog comparator interface - acifb acan3 - acan0 negative inputs for comparators "a" analog acap3 - acap0 positive inputs for comparators "a" analog acbn3 - acbn0 negative inputs for comparators "b" analog acbp3 - acbp0 positive inputs for comparators "b" analog acrefn common negative reference analog adc interface - adcifb ad8 - ad0 analog signal analog adp1 - adp0 drive pin for resistive touch screen output trigger external trigger input awire - aw data awire data i/o dataout awire data output for 2-pin mode i/o capacitive touch module - cat csa16 - csa0 capacitive sense a i/o csb16 - csb0 capacitive sense b i/o dis discharge current control analog smp smp signal output sync synchronize signal input vdiven voltage divider enable output external interrup t controller - eic nmi (extint0) non-maskable interrupt input extint5 - extint1 exte rnal interrupt input glue logic controller - gloc in7 - in0 inputs to lookup tables input out1 - out0 outputs from lookup tables output jtag module - jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input
14 32145bs?01/2012 at32uc3l0128/256 power manager - pm reset_n reset input low pulse width modulation controller - pwma pwma35 - pwma0 pwma channel waveforms output pwmaod35 - pwmaod0 pwma channel waveforms, open drain mode output not all channels support open drain mode system control interface - scif gclk4 - gclk0 generic clock output output gclk_in1 - gclk_in0 generic clock input input rc32out rc32k output at startup output xin0 crystal 0 input analog/ digital xin32 crystal 32 inpu t (primary location) analog/ digital xin32_2 crystal 32 input (secondary location) analog/ digital xout0 crystal 0 output analog xout32 crystal 32 output (primary location) analog xout32_2 crystal 32 output (secondary location) analog serial peripheral interface - spi miso master in slave out i/o mosi master out slave in i/o npcs3 - npcs0 spi peripheral chip select i/o low sck clock i/o timer/counter - tc0, tc1 a0 channel 0 line a i/o a1 channel 1 line a i/o a2 channel 2 line a i/o b0 channel 0 line b i/o b1 channel 1 line b i/o b2 channel 2 line b i/o clk0 channel 0 external clock input input clk1 channel 1 external clock input input clk2 channel 2 external clock input input two-wire interface - twims0, twims1 twalm smbus smbalert i/o low twck two-wire serial clock i/o twd two-wire serial data i/o table 3-7. signal descriptions list
15 32145bs?01/2012 at32uc3l0128/256 note: 1. adcifb: ad3 does not exist. universal synchronous asynchronous receiver transmitter - usart0, usart1, usart2, usart3 clk clock i/o cts clear to send input low rts request to send output low rxd receive data input txd transmit data output table 3-7. signal descriptions list table 3-8. signal description list, continued signal name function type active level comments power vddcore core power supply / voltage regulator output power input/output 1.62v to 1.98v vddio i/o power supply power input 1.62v to 3.6v. vddio should always be equal to or lower than vddin. vddana analog power supply power input 1.62v to 1.98v advrefp analog reference voltage power input 1.62v to 1.98v vddin voltage regulator input power input 1.62v to 3.6v (1) gndana analog ground ground gnd ground ground auxiliary port - aux mcko trace data output clock output mdo5 - mdo0 trace data output output mseo1 - mseo0 trace frame control output evti_n event in input low evto_n event out output low general purpose i/o pin pa22 - pa00 parallel i/o controller i/o port 0 i/o pb12 - pb00 parallel i/o controller i/o port 1 i/o 1. see section 6.1 on page 36
16 32145bs?01/2012 at32uc3l0128/256 3.4 i/o line considerations 3.4.1 jtag pins the jtag is enabled if tck is low while the reset_n pin is re leased. the tck, tms, and tdi pins have pull-up resistors when jtag is enabled. the tck pin always has pull-up enabled dur- ing reset. the tdo pin is an output, driven at vddio, and has no pull-up resistor. the jtag pins can be used as gpio pins and multiplex ed with peripherals when the jtag is disabled. please refer to section 3.2.4 on page 11 for the jtag port connections. 3.4.2 pa00 note that pa00 is multiplexed with tck. pa00 gpio function must only be used as output in the application. 3.4.3 reset_n pin the reset_n pin is a schmitt input and integrates a permanent pull-up resistor to vddin. as the product integrates a power-on reset detector, the reset_n pin can be left unconnected in case no reset from the system nee ds to be applied to the product. the reset_n pin is also used for the awire de bug protocol. when the pin is used for debug- ging, it must not be driven by external circuitry. 3.4.4 twi pins pa21/pb04/pb05 when these pins are used for twi, the pins are open-drain outputs with slew-rate limitation and inputs with spike filtering. when used as gpio pins or used for other peripherals, the pins have the same characteristics as other gpio pins. sele cted pins are also smbus compliant (refer to section 3.2.1 on page 8 ). as required by the smbus specification, these pins provide no leakage path to ground when the at32uc3l0128/256 is powered down. this allows other devices on the smbus to continue communicating even though the at32uc3l0128/256 is not powered. after reset a twi function is selected on these pins instead of the gpio. please refer to the gpio module configuration chapter for details. 3.4.5 twi pins pa05/pa07/pa17 when these pins are used for twi, the pins are open-drain outputs with slew-rate limitation and inputs with spike filtering. when used as gpio pins or used for other peripherals, the pins have the same characteristics as other gpio pins. after reset a twi function is selected on these pins instead of the gpio. please refer to the gpio module configuration chapter for details. 3.4.6 gpio pins all the i/o lines integrate a pull-up resistor . programming of this pull-up resistor is performed independently for each i/o line through the gpio controllers. after reset, i/o lines default as inputs with pull-up resistors disabled, except pa00 which has the pull-up resistor enabled. pa20 selects scif-rc32out (gpio function f) as default enabled after reset. 3.4.7 high-drive pins the five pins pa02, pa06, pa08, pa09, and pb01 have high-drive output capabilities. refer to section 7. on page 41 for electrical characteristics.
17 32145bs?01/2012 at32uc3l0128/256 3.4.8 rc32out pin 3.4.8.1 clock output at startup after power-up, the clock generated by the 32khz rc oscillator (rc32k) will be output on pa20, even when the device is still reset by the powe r-on reset circuitry. this clock can be used by the system to start other devices or to clock a switching regulator to rise the power supply volt- age up to an acceptable value. the clock will be available on pa20, but will be di sabled if one of the following conditions are true: ? pa20 is configured to use a gpio function other than f (scif-rc32out) ? pa20 is configured as a general purpose input/output (gpio) ? the bit frc32 in the power manager ppcr register is written to zero (refer to the power manager chapter) the maximum amplitude of the clock signal will be defined by vddin. once the rc32k output on pa20 is disabled it can never be enabled again. 3.4.8.2 xout32_2 function pa20 selects rc32out as default enabled after reset. this function is not automatically dis- abled when the user enables the xout32_2 function on pa20. this disturbs the oscillator and may result in the wrong frequency. to avoid this, rc32out must be disabled when xout32_2 is enabled. 3.4.9 adc input pins these pins are regular i/o pins powered from the vddio. however, when these pins are used for adc inputs, the voltage applied to the pin must not exceed 1.98v. internal circuitry ensures that the pin cannot be used as an analog input pin when the i/o drives to vdd. when the pins are not used for adc inputs, the pins may be driven to the full i/o voltage range.
18 32145bs?01/2012 at32uc3l0128/256 4. processor and architecture rev: 2.1.2.0 this chapter gives an overview of the avr32uc cpu. avr32uc is an implementation of the avr32 architecture. a summary of the programming model, instruction set, and mpu is pre- sented. for further details, see the avr32 architecture manual and the avr32uc technical reference manual . 4.1 features ? 32-bit load/store avr32a risc architecture ? 15 general-purpose 32-bit registers ? 32-bit stack pointer, program counter and link register reside in register file ? fully orthogonal instruction set ? privileged and unprivileged modes enabling efficient and secure operating systems ? innovative instruction set together with variable instruction length ensu ring industry leading code density ? dsp extension with saturating arithmetic, and a wide variety of multiply instructions ? 3-stage pipeline allowing one instruction per clock cy cle for most instructions ? byte, halfword, word, and double word memory access ? multiple interrupt priority levels ? mpu allows for operating s ystems with memory protection ? secure state for supporting flashvault technology 4.2 avr32 architecture avr32 is a new, high-performance 32-bit risc mi croprocessor architectu re, designed for cost- sensitive embedded applications, with particul ar emphasis on low power consumption and high code density. in addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the avr32 to be implemented as low-, mid-, or high-performance processors. avr32 extends the avr family into the world of 32- and 64-bit applications. through a quantitative approach, a large set of industry recognized benchmarks has been com- piled and analyzed to achieve the best code density in its class. in addition to lowering the memory requirements, a compact code size also contributes to the core?s low power characteris- tics. the processor supports byte and halfword data types without penalty in code size and performance. memory load and store operations are provided for byte, halfword, word, and double word data with automatic sign- or zero extension of halfw ord and byte data. the c-compiler is closely linked to the architecture and is able to expl oit code optimization features, both for size and speed. in order to reduce code size to a minimum, so me instructions have multiple addressing modes. as an example, instructions with immediates often have a compact format with a smaller imme- diate, and an extended format with a larger immediate. in this way, the compiler is able to use the format giving the smallest code size. another feature of the instruction set is that frequently used instructions, like add, have a com- pact format with two operands as well as an extended format with three operands. the larger format increases performance, allowing an addition and a data move in the same instruction in a
19 32145bs?01/2012 at32uc3l0128/256 single cycle. load and store instructions have seve ral different formats in order to reduce code size and speed up execution. the register file is organized as sixteen 32-bi t registers and includes the program counter, the link register, and the stack pointer. in addition, register r12 is designed to hold return values from function calls and is used im plicitly by some instructions. 4.3 the avr32uc cpu the avr32uc cpu targets low- and mediu m-performance applications, and provides an advanced on-chip debug (ocd) system, no caches, and a memory protection unit (mpu). java acceleration hardware is not implemented. avr32uc provides three memory interfaces, one high speed bus master for instruction fetch, one high speed bus master for data access, an d one high speed bus slave interface allowing other bus masters to access data rams internal to the cpu. keeping data rams internal to the cpu allows fast access to the rams, reduces latency, and guarantees deterministic timing. also, power consumption is reduced by not needing a full high speed bus access for memory accesses. a dedicated data ram interface is prov ided for communicating with the internal data rams. a local bus interface is provided for connecting the cpu to device-specific high-speed systems, such as floating-point units and i/o controller port s. this local bus has to be enabled by writing a one to the locen bit in the cpucr system regi ster. the local bus is able to transfer data between the cpu and the local bus slave in a single clock cycle. the local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions. details on which devices that are mapped into the local bus space is given in the cpu local bus section in the memories chapter. figure 4-1 on page 20 displays the contents of avr32uc.
20 32145bs?01/2012 at32uc3l0128/256 figure 4-1. overview of the avr32uc cpu 4.3.1 pipeline overview avr32uc has three pipeline stages, instruction fetch (if), instruction decode (id), and instruc- tion execute (ex). the ex stage is split into three parallel subsections, one arithmetic/logic (alu) section, one multiply (mul) sect ion, and one load/store (ls) section. instructions are issued and complete in order. certain operations require several clock cycles to complete, and in this case, the instruction resides in the id and ex stages for the required num- ber of clock cycles. since there is only three pipeline stages, no inte rnal data forwarding is required, and no data dependencies can arise in the pipeline. figure 4-2 on page 21 shows an overview of the avr32uc pipeline stages. avr32uc cpu pipeline instruction memory controller mpu high speed bus high speed bus ocd system ocd interface interrupt controller interface high speed bus slave high speed bus high speed bus master power/ reset control reset interface cpu local bus master cpu local bus data memory controller cpu ram high speed bus master
21 32145bs?01/2012 at32uc3l0128/256 figure 4-2. the avr32uc pipeline 4.3.2 avr32a microarchitecture compliance avr32uc implements an avr32a microarchitecture. the avr32a microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. this microarchitecture does not provide dedicated hard ware registers for shadowing of register file registers in interrupt contexts. additionally, it does not provide hardware registers for the return address registers and return status registers. instead, all this information is stored on the system stack. this saves chip area at the expense of slower interrupt handling. 4.3.2.1 interrupt handling upon interrupt initiation, registers r8-r12 are automatically pushed to the system stack. these registers are pushed regardless of the priority level of the pending interrupt. the return address and status register are also automatically pushed to stack. the interrupt handler can therefore use r8-r12 freely. upon interrupt completion, the old r8-r12 registers and status register are restored, and execution continues at the return address stored popped from stack. the stack is also used to store the status register and return address for exceptions and scall . executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address. 4.3.2.2 java support avr32uc does not provide java hardware acceleration. 4.3.2.3 memory protection the mpu allows the user to check all memory accesses for privilege violations. if an access is attempted to an illegal memory address, the access is aborted and an exception is taken. the mpu in avr32uc is specified in t he avr32uc technical reference manual. 4.3.2.4 unaligned reference handling avr32uc does not support unaligned accesses, except for doubleword accesses. avr32uc is able to perform word-aligned st.d and ld.d . any other unaligned memory access will cause an if id alu mul regfile write prefetch unit decode unit alu unit multiply unit load-store unit ls regfile read
22 32145bs?01/2012 at32uc3l0128/256 address exception. doubleword -sized accesses with word-align ed pointers will automatically be performed as two word-sized accesses. the following table shows the instructions with support for unaligned addresses. all other instructions requir e aligned addresses. 4.3.2.5 unimplemented instructions the following instructions are unimplemented in avr32uc, and will cause an unimplemented instruction exception if executed: ? all simd instructions ? all coprocessor instructions if no coprocessors are present ? retj, incjosp, popjc, pushjc ? tlbr, tlbs, tlbw ? cache 4.3.2.6 cpu and architecture revision three major revisions of the avr32uc cpu currently exist. the device described in this datasheet uses cpu revision 3. the architecture revision field in the config0 system register identifies which architecture revision is implemented in a specific device. avr32uc cpu revision 3 is fully backward-compatibl e with revisions 1 and 2, ie. code compiled for revision 1 or 2 is binary-compatible with revision 3 cpus. table 4-1. instructions with una ligned reference support instruction supported alignment ld.d word st.d word
23 32145bs?01/2012 at32uc3l0128/256 4.4 programming model 4.4.1 register file configuration the avr32uc register file is shown below. figure 4-3. the avr32uc register file 4.4.2 status register configuration the status register (sr) is split into two halfwords, one upper and one lower, see figure 4-4 and figure 4-5 . the lower word contains the c, z, n, v, and q condition code flags and the r, t, and l bits, while the upper halfword contains information about the mode and state the proces- sor executes in. refer to the avr32 architecture manual for details. figure 4-4. the status register high halfword application bit 0 supervisor bit 31 pc sr int0pc fintpc int1pc smpc r7 r5 r6 r4 r3 r1 r2 r0 bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 int0 sp_app sp_sys r12 r11 r9 r10 r8 exception nmi int1 int2 int3 lr lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr secure bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sec lr ss_status ss_adrf ss_adrr ss_adr0 ss_adr1 ss_sp_sys ss_sp_app ss_rar ss_rsr bit 31 0 0 0 bit 16 interrupt level 0 mask interrupt level 1 mask interrupt level 3 mask interrupt level 2 mask 1 0 0 0 0 1 1 0 0 0 0 0 0 fe i0m gm m1 - d m0 em i2m dm - m2 lc 1 ss initial value bit name i1m mode bit 0 mode bit 1 - mode bit 2 reserved debug state - i3m reserved exception mask global interrupt mask debug state mask secure state
24 32145bs?01/2012 at32uc3l0128/256 figure 4-5. the status register low halfword 4.4.3 processor states 4.4.3.1 normal risc state the avr32 processor supports several diff erent execution contexts as shown in table 4-2 . mode changes can be made under software control, or can be caused by external interrupts or exception processing. a mode can be interrupted by a higher priority mode, but never by one with lower priority. nested exceptions can be supported with a minimal software overhead. when running an operating system on the avr32, user processes will typically execute in the application mode. the programs executed in this mode are restricted from executing certain instructions. furthermore, most system registers together with the upper halfword of the status register cannot be accessed. protected memory areas are also not available. all other operating modes are privileged and are collectively called system modes. they have full access to all priv- ileged and unprivileged re sources. after a reset, the proc essor will be in su pervisor mode. 4.4.3.2 debug state the avr32 can be set in a debug state, which allows implementation of software monitor rou- tines that can read out and alter system information for use during application development. this implies that all system and application regist ers, including the status registers and program counters, are accessible in debug state. th e privileged instructions are also available. all interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. bit 15 bit 0 reserved carry zero sign 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - t - bit name initial value 0 0 l q v n z c - overflow saturation - - - lock reserved scratch table 4-2. overview of execution modes, thei r priorities and privilege levels. priority mode securi ty description 1 non maskable interrupt privileged non maskable high priority interrupt mode 2 exception privileged execute exceptions 3 interrupt 3 privileged general purpose interrupt mode 4 interrupt 2 privileged general purpose interrupt mode 5 interrupt 1 privileged general purpose interrupt mode 6 interrupt 0 privileged general purpose interrupt mode n/a supervisor privileged runs supervisor calls n/a application unprivileged normal program execution mode
25 32145bs?01/2012 at32uc3l0128/256 debug state can be entered as described in the avr32uc technical reference manual . debug state is exited by the retd instruction. 4.4.3.3 secure state the avr32 can be set in a secure state, that allows a part of the code to execute in a state with higher security levels. the rest of the code can not access resources reserved for this secure code. secure state is used to implemen t flashvault technology. refer to the avr32uc techni- cal reference manual for details. 4.4.4 system registers the system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. the table below lis ts the system registers speci- fied in the avr32 architecture, some of which are unused in avr32uc. the programmer is responsible for maintaining correct sequen cing of any instructions following a mtsr instruction. for detail on the system registers, refer to the avr32uc technical reference manual . table 4-3. system registers reg # address name function 0 0 sr status register 1 4 evba exception vector base address 2 8 acba application call base address 3 12 cpucr cpu control register 4 16 ecr exception cause register 5 20 rsr_sup unused in avr32uc 6 24 rsr_int0 unused in avr32uc 7 28 rsr_int1 unused in avr32uc 8 32 rsr_int2 unused in avr32uc 9 36 rsr_int3 unused in avr32uc 10 40 rsr_ex unused in avr32uc 11 44 rsr_nmi unused in avr32uc 12 48 rsr_dbg return status register for debug mode 13 52 rar_sup unused in avr32uc 14 56 rar_int0 unused in avr32uc 15 60 rar_int1 unused in avr32uc 16 64 rar_int2 unused in avr32uc 17 68 rar_int3 unused in avr32uc 18 72 rar_ex unused in avr32uc 19 76 rar_nmi unused in avr32uc 20 80 rar_dbg return address register for debug mode 21 84 jecr unused in avr32uc 22 88 josp unused in avr32uc 23 92 java_lv0 unused in avr32uc
26 32145bs?01/2012 at32uc3l0128/256 24 96 java_lv1 unused in avr32uc 25 100 java_lv2 unused in avr32uc 26 104 java_lv3 unused in avr32uc 27 108 java_lv4 unused in avr32uc 28 112 java_lv5 unused in avr32uc 29 116 java_lv6 unused in avr32uc 30 120 java_lv7 unused in avr32uc 31 124 jtba unused in avr32uc 32 128 jbcr unused in avr32uc 33-63 132-252 reserved reserved for future use 64 256 config0 configuration register 0 65 260 config1 configuration register 1 66 264 count cycle counter register 67 268 compare compare register 68 272 tlbehi unused in avr32uc 69 276 tlbelo unused in avr32uc 70 280 ptbr unused in avr32uc 71 284 tlbear unused in avr32uc 72 288 mmucr unused in avr32uc 73 292 tlbarlo unused in avr32uc 74 296 tlbarhi unused in avr32uc 75 300 pccnt unused in avr32uc 76 304 pcnt0 unused in avr32uc 77 308 pcnt1 unused in avr32uc 78 312 pccr unused in avr32uc 79 316 bear bus error address register 80 320 mpuar0 mpu address register region 0 81 324 mpuar1 mpu address register region 1 82 328 mpuar2 mpu address register region 2 83 332 mpuar3 mpu address register region 3 84 336 mpuar4 mpu address register region 4 85 340 mpuar5 mpu address register region 5 86 344 mpuar6 mpu address register region 6 87 348 mpuar7 mpu address register region 7 88 352 mpupsr0 mpu privilege select register region 0 89 356 mpupsr1 mpu privilege select register region 1 table 4-3. system registers (continued) reg # address name function
27 32145bs?01/2012 at32uc3l0128/256 4.5 exceptions and interrupts in the avr32 architecture, events are used as a common term for exceptions and interrupts. avr32uc incorporates a powerful event handling scheme. the different event sources, like ille- gal op-code and interrupt requests, have different priority levels, ensuring a well-defined behavior when multiple events are received simultaneously. additionally, pending events of a higher priority class may preempt handling of ongoing events of a lower priority class. when an event occurs, the execution of the instru ction stream is halted, and execution is passed to an event handler at an address specified in table 4-4 on page 31 . most of the handlers are placed sequentially in the code sp ace starting at the ad dress specified by evba, with four bytes between each handler. this gives ample space for a jump instruction to be placed there, jump- ing to the event routine itself. a few critical handlers have larg er spacing between them, allowing the entire event routine to be placed directly at the address specified by the evba-relative offset generated by hardware. all interrupt sources have autovectored interrupt service routine (isr) addresses. this allows the interrupt controller to directly specify the isr address as an address 90 360 mpupsr2 mpu privilege select register region 2 91 364 mpupsr3 mpu privilege select register region 3 92 368 mpupsr4 mpu privilege select register region 4 93 372 mpupsr5 mpu privilege select register region 5 94 376 mpupsr6 mpu privilege select register region 6 95 380 mpupsr7 mpu privilege select register region 7 96 384 mpucra unused in this version of avr32uc 97 388 mpucrb unused in this version of avr32uc 98 392 mpubra unused in this version of avr32uc 99 396 mpubrb unused in this version of avr32uc 100 400 mpuapra mpu access permission register a 101 404 mpuaprb mpu access permission register b 102 408 mpucr mpu control register 103 412 ss_status secure state status register 104 416 ss_adrf secure state address flash register 105 420 ss_adrr secure state address ram register 106 424 ss_adr0 secure state address 0 register 107 428 ss_adr1 secure state address 1 register 108 432 ss_sp_sys secure state stack pointer system register 109 436 ss_sp_app secure state stac k pointer application register 110 440 ss_rar secure state return address register 111 444 ss_rsr secure state return status register 112-191 448-764 reserved reserved for future use 192-255 768-1020 impl implementation defined table 4-3. system registers (continued) reg # address name function
28 32145bs?01/2012 at32uc3l0128/256 relative to evba. the autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. the target address of the event handle r is calculated as (evba | event_handler_offset), not (evba + event_handler_offse t), so evba and exception code segments must be set up appropriately. the same mechanisms are used to service all different types of events, including interrupt requests, yielding a uniform event handling scheme. an interrupt controller does the priority handling of the interrupts and provides the autovector off- set to the cpu. 4.5.1 system stack issues event handling in avr32uc uses the system stack pointed to by the system stack pointer, sp_sys, for pushing and popping r8 -r12, lr, status register, and return ad dress. since event code may be timing-critical, sp_sys should point to memory addresses in the iram section, since the timing of accesses to this memory section is both fast and deterministic. the user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. if the system stack is full, and an event occurs, the system will enter an undefined state. 4.5.2 exceptions and interrupt requests when an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. the pending event will not be acce pted if it is masked. the i3 m, i2m, i1m, i0m, em, and gm bits in the status register are used to mask different events. not all events can be masked. a few critical events (nmi, unreco verable exception, tlb multiple hit, and bus error) can not be masked. when an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. this inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. it is the event source?s respons- ability to ensure that their events are left pending until accepted by the cpu. 2. when a request is accepted, the status register and program counter of the current context is stored to the system stack. if the event is an int0, int1, int2, or int3, reg- isters r8-r12 and lr are also automatically stored to stack. storing the status register ensures that the core is returned to the previous execution mode when the current event handling is completed. when exceptions occur, both the em and gm bits are set, and the application may manually enable nested exceptions if desired by clear- ing the appropriate bit. each exception handler has a dedicated handler address, and this address uniquely identifies the exception source. 3. the mode bits are set to reflect the priority of the accepted event, and the correct regis- ter file bank is selected. the address of the event handler, as shown in table 4-4 on page 31 , is loaded into the program counter. the execution of the event handler routine then continues from the effective address calculated. the rete instruction signals the end of the event. when encountered, the return status register and return address register are popped from the system stack and restored to the status reg- ister and program counter. if the rete instruction returns from int0, int1, int2, or int3, registers r8-r12 and lr are also popped from the system stack. the restored status register contains information allowing the core to resume operation in the previous execution mode. this concludes the event handling.
29 32145bs?01/2012 at32uc3l0128/256 4.5.3 supervisor calls the avr32 instruction set provides a supervisor mode call instruction. the scall instruction is designed so that privileged routines can be called from any context. this facilitates sharing of code between different execution modes. the scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from time- critical event handlers. the scall instruction behaves differently depending on which mode it is called from. the behav- iour is detailed in the instruction se t reference. in order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets , is implemented. in the avr32uc cpu, scall and rets uses the system stack to store the return address and the status register. 4.5.4 debug requests the avr32 architecture defines a dedicated debug mode. when a debug request is received by the core, debug mode is entered. entry into debug mode can be masked by the dm bit in the status register. upon entry into debug mode, hardware sets the sr.d bit and jumps to the debug exception handler. by default, debug mode executes in the exception context, but with dedicated return address register and return status register. these dedicated registers remove the need for storing this data to the system stack, t hereby improving debuggability. the mode bits in the status register can freely be manipulated in debug mode, to observe registers in all contexts, while retaining full privileges. debug mode is exited by executing the retd instruction. this return s to the previous context. 4.5.5 entry points for events several different event handler entry points exist. in avr32uc, the reset address is 0x80000000. this places the reset address in the boot flash memory area. tlb miss exceptions and scall have a dedicated space relative to evba where their event han- dler can be placed. this speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. all other exceptions have a dedicated event routine entry point located relative to evba. the handler routine address identifies the exception source directly. avr32uc uses the itlb and dtlb protection exc eptions to signal a mp u protection violation. itlb and dtlb miss exceptions are used to signal that an access address did not map to any of the entries in the mpu. tlb multiple hit exception indicates that an access address did map to multiple tlb entries, signalling an error. all interrupt requests have entry points located at an offset relative to evba. this autovector off- set is specified by an interrupt controller. the programmer must make sure that none of the autovector offsets interfere with the placement of other code. the autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. special considerations should be made when loading evba with a po inter. due to security con- siderations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an mpu is present. if several events occur on the same instruction, they are handled in a prioritized way. the priority ordering is presented in table 4-4 on page 31 . if events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority
30 32145bs?01/2012 at32uc3l0128/256 than the oldest instruction. an instruction b is younger than an instruction a if it was sent down the pipeline later than a. the addresses and priority of simultaneous events are shown in table 4-4 on page 31 . some of the exceptions are unused in avr32uc since it has no mmu, coprocessor interface, or floating- point unit.
31 32145bs?01/2012 at32uc3l0128/256 table 4-4. priority and handler addresses for events priority handler address name event source stored return address 1 0x80000000 reset external input undefined 2 provided by ocd system ocd stop cpu ocd system first non-compl eted instruction 3 evba+0x00 unrecoverable exception int ernal pc of offending instruction 4 evba+0x04 tlb multiple hit mpu pc of offending instruction 5 evba+0x08 bus error data fetch data bu s first non-completed instruction 6 evba+0x0c bus error instruction fetch dat a bus first non-completed instruction 7 evba+0x10 nmi external input first non-completed instruction 8 autovectored interrupt 3 request external input first non-completed instruction 9 autovectored interrupt 2 request external input first non-completed instruction 10 autovectored interrupt 1 request external input first non-completed instruction 11 autovectored interrupt 0 request external input first non-completed instruction 12 evba+0x14 instruction address cp u pc of offending instruction 13 evba+0x50 itlb miss mpu pc of offending instruction 14 evba+0x18 itlb protection mpu pc of offending instruction 15 evba+0x1c breakpoint ocd system firs t non-completed instruction 16 evba+0x20 illegal opcode instructio n pc of offending instruction 17 evba+0x24 unimplemented instruction instr uction pc of offending instruction 18 evba+0x28 privilege violation instruc tion pc of offending instruction 19 evba+0x2c floating-point unused 20 evba+0x30 coprocessor absent instruct ion pc of offending instruction 21 evba+0x100 supervisor call instru ction pc(supervisor call) +2 22 evba+0x34 data address (read) cp u pc of offending instruction 23 evba+0x38 data address (write) cpu pc of offending instruction 24 evba+0x60 dtlb miss (read) mpu pc of offending instruction 25 evba+0x70 dtlb miss (write) mpu pc of offending instruction 26 evba+0x3c dtlb protection (read) mpu pc of offending instruction 27 evba+0x40 dtlb protection (write) m pu pc of offending instruction 28 evba+0x44 dtlb modified unused
32 32145bs?01/2012 at32uc3l0128/256 5. memories 5.1 embedded memories ? internal high-speed flash ? 256kbytes (at32uc3l0256) ? 128kbytes (at32uc3l0128) ? 0 wait state access at up to 25mhz in worst case conditions ? 1 wait state access at up to 50mhz in worst case conditions ? pipelined flash architecture, allowing burst r eads from sequen tial flash loca tions, hiding penalty of 1 wait state access ? pipelined flash architecture typically reduce s the cycle penalty of 1 wait state operation to only 8% compared to 0 wait state operation ? 100 000 write cycles, 15-year data retention capability ? sector lock capabilities, boot loader protection, security bit ? 32 fuses, erased during chip erase ? user page for data to be preserved during chip erase ? internal high-speed sram, sing le-cycle access at full speed ?32kbytes 5.2 physical memory map the system bus is implemented as a bus matrix . all system bus addresses are fixed, and they are never remapped in any way, not even during boot. note that avr32 uc cpu uses unseg- mented translation, as described in the avr32 ar chitecture manual. the 32-bit physical address space is mapped as follows: table 5-1. at32uc3l0128/256 physical memory map device start address size at32uc3l0256 at32uc3l0128 embedded sram 0x00000000 32kbytes 32kbytes embedded flash 0x80000000 256kbytes 128kbytes sau channels 0x90000000 256 bytes 256 bytes hsb-pb bridge b 0xfffe0000 64kbytes 64kbytes hsb-pb bridge a 0xffff0000 64kbytes 64kbytes table 5-2. flash memory parameters part number flash size ( flash_pw ) number of pages ( flash_p ) page size ( flash_w ) at32uc3l0256 256kbytes 512 512bytes at32uc3l0128 128kbytes 256 512bytes
33 32145bs?01/2012 at32uc3l0128/256 5.3 peripheral address map table 5-3. peripheral address mapping address peripheral name 0xfffe0000 flashcdw flash controller - flashcdw 0xfffe0400 hmatrix hsb matrix - hmatrix 0xfffe0800 sau secure access unit - sau 0xffff0000 pdca peripheral dma controller - pdca 0xffff1000 intc interrupt controller - intc 0xffff1400 pm power manager - pm 0xffff1800 scif system control interface - scif 0xffff1c00 ast asynchronous timer - ast 0xffff2000 wdt watchdog timer - wdt 0xffff2400 eic external interrupt controller - eic 0xffff2800 freqm frequency meter - freqm 0xffff2c00 gpio general-purpose input/output controller - gpio 0xffff3000 usart0 universal synchronous asynchronous receiver transmitter - usart0 0xffff3400 usart1 universal synchronous asynchronous receiver transmitter - usart1 0xffff3800 usart2 universal synchronous asynchronous receiver transmitter - usart2 0xffff3c00 usart3 universal synchronous asynchronous receiver transmitter - usart3 0xffff4000 spi serial peripheral interface - spi 0xffff4400 twim0 two-wire master interface - twim0
34 32145bs?01/2012 at32uc3l0128/256 5.4 cpu local bus mapping some of the registers in the gpio module are mapped onto the cpu local bus, in addition to being mapped on the peripheral bus. these registers can therefore be reached both by accesses on the peripheral bus, and by accesses on the local bus. mapping these registers on the local bus allows cycle-deterministic toggling of gpio pins since the cpu and gpio are the only modules connected to this bus. also, since the local bus runs at cpu speed, one write or read operation can be pe rformed per clock cycle to the local bus- mapped gpio registers. 0xffff4800 twim1 two-wire master interface - twim1 0xffff4c00 twis0 two-wire slave interface - twis0 0xffff5000 twis1 two-wire slave interface - twis1 0xffff5400 pwma pulse width modulation controller - pwma 0xffff5800 tc0 timer/counter - tc0 0xffff5c00 tc1 timer/counter - tc1 0xffff6000 adcifb adc interface - adcifb 0xffff6400 acifb analog comparator interface - acifb 0xffff6800 cat capacitive touch module - cat 0xffff6c00 gloc glue logic controller - gloc 0xffff7000 aw awire - aw table 5-3. peripheral address mapping
35 32145bs?01/2012 at32uc3l0128/256 the following gpio registers are mapped on the local bus: table 5-4. local bus mapped gpio registers port register mode local bus address access 0 output driver enable register (oder) write 0x40000040 write-only set 0x40000044 write-only clear 0x40000048 write-only toggle 0x4000004c write-only output value register (ovr) write 0x40000050 write-only set 0x40000054 write-only clear 0x40000058 write-only toggle 0x4000005c write-only pin value register (pvr) - 0x40000060 read-only 1 output driver enable register (oder) write 0x40000140 write-only set 0x40000144 write-only clear 0x40000148 write-only toggle 0x4000014c write-only output value register (ovr) write 0x40000150 write-only set 0x40000154 write-only clear 0x40000158 write-only toggle 0x4000015c write-only pin value register (pvr) - 0x40000160 read-only
36 32145bs?01/2012 at32uc3l0128/256 6. supply and startup considerations 6.1 supply considerations 6.1.1 power supplies the at32uc3l0128/256 has several types of power supply pins: ?vddio: powers i/o lines. voltage is 1.8 to 3.3v nominal. ?vddin: powers i/o lines and the internal regulator. voltage is 1.8 to 3.3v nominal. ?vddana: powers the adc. voltage is 1.8v nominal. ?vddcore: powers the core, memories, and peripherals. voltage is 1.8v nominal. the ground pins gnd are common to vddcore, vddio, and vddin. the ground pin for vddana is gndana. when vddcore is not connected to vddin, t he vddin voltage must be higher than 1.98v. refer to section 7. on page 41 for power consumption on the various supply pins. for decoupling recommendations for the different power supplies, please refer to the schematic checklist. refer to section 3.2 on page 8 for power supply connections for i/o pins. 6.1.2 voltage regulator the at32uc3l0128/256 embeds a voltage regulator that converts from 3.3v nominal to 1.8v with a load of up to 60ma. the regulator supplies the output voltage on vddcore. the regula- tor may only be used to drive internal circuitr y in the device. vddcore should be externally connected to the 1.8v domains. see section 6.1.3 for regulator connection figures. adequate output supply decoupling is mandat ory for vddcore to reduce ripple and avoid oscillations. the best way to achieve this is to use two capacitors in parallel between vddcore and gnd as close to the device as possible. please refer to section 7.8.1 on page 55 for decou- pling capacitors values and regulator characteristics. figure 6-1. supply decoupling the voltage regulator can be turned off in the shutdown mode to power down the core logic and keep a small part of the system powered in order to reduce power consumption. to enter this mode the 3.3v supply mode, with 1.8v regulated i/o lines power supply configuration must be used. 3.3v 1.8v vddin vddcore 1.8v regulator c in1 c out1 c out2 c in2 in3 c
37 32145bs?01/2012 at32uc3l0128/256 6.1.3 regulator connection the at32uc3l0128/256 supports three power supply configurations: ? 3.3v single supply mode ? shutdown mode is not available ? 1.8v single supply mode ? shutdown mode is not available ? 3.3v supply mode, with 1.8v regulated i/o lines ? shutdown mode is available 6.1.3.1 3.3v single supply mode in 3.3v single supply mode the internal regulator is connected to the 3.3v source (vddin pin) and its output feeds vddcore. figure 6-2 shows the power schematics to be used for 3.3v single supply mode. all i/o lines will be po wered by the same power (vddin=vddio). figure 6-2. 3.3v single supply mode vddio vddcore + - 1.98-3.6v vddana adc vddin gnd gndana cpu, peripherals, memories, scif, bod, rcsys, dfll, pll osc32k, rc32k, por33, sm33 i/o pins i/o pins osc32k_2, ast, wake, regulator control linear regulator
38 32145bs?01/2012 at32uc3l0128/256 6.1.3.2 1.8 v single supply mode in 1.8v single supply mode the internal regul ator is not used, and vddio and vddcore are powered by a single 1.8 v supply as shown in figure 6-3 . all i/o lines will be powered by the same power (vddin = vddio = vddcore). figure 6-3. 1.8v single supply mode. vddio vddcore + - 1.62-1.98v vddana adc vddin gnd gndana cpu, peripherals, memories, scif, bod, rcsys, dfll, pll osc32k, rc32k, por33, sm33 i/o pins i/o pins osc32k_2, ast, wake, regulator control
39 32145bs?01/2012 at32uc3l0128/256 6.1.3.3 3.3v supply mode with 1.8 v regulated i/o lines in this mode, the internal regulator is connecte d to the 3.3v source and its output is connected to both vddcore and vddio as shown in figure 6-4 . this configuration is required in order to use shutdown mode. figure 6-4. 3.3v supply mode with 1.8v regulated i/o lines in this mode, some i/o lines are powered by v ddin while other i/o lines are powered by vddio. refer to section 3.2.1 on page 8 for description of power supply for each i/o line. refer to the power manager chapter for a description of what parts of the system are powered in shutdown mode. important note: as the regulator has a maximum output current of 60 ma, this mode can only be used in applications where the maximum i/o current is known and compatible with the core and peripheral power consumption. typically, great care must be used to ensure that only a few i/o lines are toggling at the same time and drive very small loads. vddio vddcore + - 1.98-3.6v vddana adc vddin gnd gndana cpu, peripherals, memories, scif, bod, rcsys, dfll, pll osc32k, rc32k, por33, sm33 i/o pins i/o pins osc32k_2, ast, wake, regulator control linear regulator
40 32145bs?01/2012 at32uc3l0128/256 6.1.4 power-up sequence 6.1.4.1 maximum rise rate to avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in table 7-3 on page 42 . recommended order for power supplies is also described in this chapter. 6.1.4.2 minimum rise rate the integrated power-on reset (por33) circuitry monitoring the vddin powering supply requires a minimum rise rate for the vddin power supply. see table 7-3 on page 42 for the minimum rise rate value. if the application can not ensure that the minimum rise rate condition for the vddin power sup- ply is met, one of the following configurations can be used: ? a logic ?0? value is applied during power-up on pin pa11 (wake_n) until vddin rises above 1.2v. ? a logic ?0? value is applied during power-up on pin reset_n until vddin rises above 1.2v. 6.2 startup considerations this chapter summarizes the boot sequence of the at32uc3l0128/256. the behavior after power-up is controlled by the power manager. for specific details, refer to the power manager chapter. 6.2.1 starting of clocks after power-up, the device will be held in a reset state by the power-on reset (por18 and por33) circuitry for a short time to allow t he power to stabilize thr oughout the device. after reset, the device will use the system rc oscillat or (rcsys) as clock source. please refer to table 7-17 on page 54 for the frequency for this oscillator. on system start-up, all high-speed clocks are disabled. all clocks to all modules are running. no clocks have a divided frequency; all parts of th e system receive a clock with the same frequency as the system rc oscillator. when powering up the device, there may be a delay before the voltage has stabilized, depend- ing on the rise time of the supply used. the cpu can start executing code as soon as the supply is above the por18 and por33 thresholds, and bef ore the supply is stable. before switching to a high-speed clock source, the user should use the bod to make sure the vddcore is above the minimum level (1.62v). 6.2.2 fetching of initial instructions after reset has been released, the avr32 uc cpu starts fetching instructions from the reset address, which is 0x80000000. this address points to the first address in the internal flash. the code read from the internal flash is free to configure the clock system and clock sources. please refer to the pm and scif chapters for more details.
41 32145bs?01/2012 at32uc3l0128/256 7. electrical characteristics 7.1 absolute maximum ratings* notes: 1. 5v tolerant pins, see section 3.2 ?peripheral multiplexing on i/o lines? on page 8 2. v vdd corresponds to either v vddin or v vddio , depending on the supply for the pin. refer to section 3.2 on page 8 for details. 7.2 supply characteristics the following characteristics are applicable to the operating temperature range: t a =-40c to 85c, unless otherwise specified and are valid for a junction temperature up to t j =100c. please refer to section 6. ?supply and startup considerations? on page 36 table 7-1. absolute maximum ratings operating temperature..................................... -40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional opera- tion of the device at these or other condi- tions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended peri- ods may affect device reliability. storage temperature...................................... -60c to +150c voltage on input pins (except for 5v pins) with respect to ground .................................................................-0.3v to v vdd (2) +0.3v voltage on 5v tolerant (1) pins with respect to ground ............... .............................................................................-0.3v to 5.5v total dc output current on all i/ o pins - vddio ........... 120ma total dc output current on all i/o pins - vddin ............. 36ma maximum operating voltage v ddcore.............. ........... 1.98v maximum operating voltage vddio, vddin .................... 3.6v table 7-2. supply characteristics symbol parameter voltag e min max unit v vddio dc supply peripheral i/os 1.62 3.6 v v vddin dc supply peripheral i/os, 1.8v single supply mode 1.62 1.98 v dc supply peripheral i/os and internal regulator, 3.3v supply mode 1.98 3.6 v v vddcore dc supply core 1.62 1.98 v v vddana analog supply voltage 1.62 1.98 v
42 32145bs?01/2012 at32uc3l0128/256 note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same process technology. t hese values are not covered by test limits in production. 7.3 maximum clock frequencies these parameters are given in the following conditions: ?v vddcore = 1.62v to 1.98v ? temperature = -40c to 85c 7.4 power consumption the values in table 7-5 are measured values of power consumption under the following condi- tions, except where noted: ? operating conditions, internal core supply ( figure 7-1 ) - this is the default configuration table 7-3. supply rise rates and order (1) symbol parameter rise rate min max unit comment v vddio dc supply peripheral i/os 0 2.5 v/s v vddin dc supply peripheral i/os and internal regulator 0.002 2.5 v/s slower rise time requires external power-on reset circuit. v vddcore dc supply core 0 2.5 v/s rise before or at the same time as vddio v vddana analog supply voltage 0 2.5 v/s rise together with vddcore table 7-4. clock frequencies symbol parameter description min max units f cpu cpu clock frequency 50 mhz f pba pba clock frequency 50 f pbb pbb clock frequency 50 f gclk0 gclk0 clock frequency dfllif main reference, gclk0 pin 50 f gclk1 gclk1 clock frequency dfllif dithering and ssg reference, gclk1 pin 50 f gclk2 gclk2 clock frequency ast, gclk2 pin 20 f gclk3 gclk3 clock frequency pwma, gclk3 pin 140 f gclk4 gclk4 clock frequency cat, acifb, gclk4 pin 50 f gclk5 gclk5 clock frequency gloc 80 f gclk6 gclk6 clock frequency 50 f gclk7 gclk7 clock frequency 50 f gclk8 gclk8 clock frequency pll source clock 50 f gclk9 gclk9 clock frequency freqm, gclk0-8 150
43 32145bs?01/2012 at32uc3l0128/256 ?v vddin = 3.0v ?v vddcore = 1.62v, supplied by the internal regulator ? corresponds to the 3.3v supply mode with 1.8v regulated i/o lines, please refer to the supply and startup considerations section for more details ? equivalent to the 3.3v single supply mode ? consumption in 1.8v single supply mode can be estimated by subtracting the regula- tor static current ? operating conditions, external core supply ( figure 7-2 ) - used only when noted ?v vddin = v vddcore = 1.8v ? corresponds to the 1.8v single supply mode, please refer to the supply and startup considerations section for more details ?t a = 25 c ? oscillators ? osc0 (crystal o scillator) stopped ? osc32k (32khz crystal oscillator) running with external 32khz crystal ? dfll running at 50mhz with osc32k as reference ? clocks ? dfll used as main clock source ? cpu, hsb, and pbb clocks undivided ? pba clock divided by 4 ? the following peripheral clocks running ? pm, scif, ast, flashcdw, pba bridge ? all other peripheral clocks stopped ? i/os are inactive with internal pull-up ? flash enabled in high speed mode ? por18 enabled ? por33 disabled
44 32145bs?01/2012 at32uc3l0128/256 note: 1. these numbers are valid for the measured condition only and must not be extrapolated to other frequencies. figure 7-1. measurement schematic, internal core supply table 7-5. power consumption for different operating modes mode conditions measured on consumption typ unit active (1) cpu running a recursive fibonacci algorithm amp0 300 a/mhz cpu running a division algorithm 174 idle (1) 96 frozen (1) 57 standby (1) 46 stop 38 a deepstop 25 static -osc32k and ast stopped -internal core supply 14 -osc32k running -ast running at 1khz -external core supply ( figure 7-2 ) 7.3 -osc32k and ast stopped -external core supply ( figure 7-2 ) 6.7 shutdown -osc32k running -ast running at 1khz 800 na ast and osc32k stopped 220 amp0 vddin vddcore vddana vddio
45 32145bs?01/2012 at32uc3l0128/256 figure 7-2. measurement schematic, external core supply amp0 vddin vddcore vddana vddio
46 32145bs?01/2012 at32uc3l0128/256 7.5 i/o pin c haracteristics notes: 1. v vdd corresponds to either v vddin or v vddio , depending on the supply for the pin. refer to section 3.2.1 on page 8 for details. 2. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. table 7-6. normal i/o pin characteristics (1) symbol parameter condition min typ max units r pullup pull-up resistance 75 100 145 kohm v il input low-level voltage v vdd = 3.0v -0.3 0.3*v vdd v v vdd = 1.62v -0.3 0.3*v vdd v ih input high-level voltage v vdd = 3.6v 0.7*v vdd v vdd + 0.3 v v vdd = 1.98v 0.7*v vdd v vdd + 0.3 v ol output low-level voltage v vdd = 3.0v, i ol = 3ma 0.4 v v vdd = 1.62v, i ol = 2ma 0.4 v oh output high-level voltage v vdd = 3.0v, i oh = 3ma v vdd - 0.4 v v vdd = 1.62v, i oh = 2ma v vdd - 0.4 f max output frequency (2) v vdd = 3.0v, load = 10pf 45 mhz v vdd = 3.0v, load = 30pf 23 t rise rise time (2) v vdd = 3.0v, load = 10pf 4.7 ns v vdd = 3.0v, load = 30pf 11.5 t fall fall time (2) v vdd = 3.0v, load = 10pf 4.8 v vdd = 3.0v, load = 30pf 12 i leak input leakage current pull-up resistors disabled 1 a c in input capacitance, all normal i/o pins except pa 0 5 , pa 0 7 , pa 1 7 , pa 2 0 , pa21, pb04, pb05 tqfp48 package 1.4 pf qfn48 package 1.1 tllga48 package 1.1 c in input capacitance, pa20 tqfp48 package 2.7 qfn48 package 2.4 tllga48 package 2.4 c in input capacitance, pa05, pa07, pa17, pa21, pb04, pb05 tqfp48 package 3.8 qfn48 package 3.5 tllga48 package 3.5 table 7-7. high-drive i/o pin characteristics (1) symbol parameter condition min typ max units r pullup pull-up resistance pa06 30 50 110 kohm pa02, pb01, reset 75 100 145 pa08, pa09 10 20 45
47 32145bs?01/2012 at32uc3l0128/256 notes: 1. v vdd corresponds to either v vddin or v vddio , depending on the supply for the pin. refer to section 3.2.1 on page 8 for details. 2. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. v il input low-level voltage v vdd = 3.0v -0.3 0.3*v vdd v v vdd = 1.62v -0.3 0.3*v vdd v ih input high-level voltage v vdd = 3.6v 0.7*v vdd v vdd + 0.3 v v vdd = 1.98v 0.7*v vdd v vdd + 0.3 v ol output low-level voltage v vdd = 3.0v, i ol = 6ma 0.4 v v vdd = 1.62v, i ol = 4ma 0.4 v oh output high-level voltage v vdd = 3.0v, i oh = 6ma v vdd -0.4 v v vdd = 1.62v, i oh = 4ma v vdd -0.4 f max output frequency, all high-drive i/o pins, except pa08 and pa09 (2) v vdd = 3.0v, load = 10pf 45 mhz v vdd = 3.0v, load = 30pf 23 t rise rise time, all high-drive i/o pins, except pa08 and pa09 (2) v vdd = 3.0v, load = 10pf 4.7 ns v vdd = 3.0v, load = 30pf 11.5 t fall fall time, all high-drive i/o pins, except pa08 and pa09 (2) v vdd = 3.0v, load = 10pf 4.8 v vdd = 3.0v, load = 30pf 12 f max output frequency, pa08 and pa 0 9 (2) v vdd = 3.0v, load = 10pf 54 mhz v vdd = 3.0v, load = 30pf 40 t rise rise time, pa08 and pa09 (2) v vdd = 3.0v, load = 10pf 2.8 ns v vdd = 3.0v, load = 30pf 4.9 t fall fall time, pa08 and pa09 (2) v vdd = 3.0v, load = 10pf 2.4 v vdd = 3.0v, load = 30pf 4.6 i leak input leakage current pull-up resistors disabled 1 a c in input capacitance, all high-drive i/o pins, except pa08 and pa09 tqfp48 package 2.2 pf qfn48 package 2.0 tllga48 package 2.0 c in input capacitance, pa08 and pa09 tqfp48 package 7.0 qfn48 package 6.7 tllga48 package 6.7 table 7-7. high-drive i/o pin characteristics (1) symbol parameter condition min typ max units table 7-8. high-drive i/o, 5v toler ant, pin characteristics (1) symbol parameter condition min typ max units r pullup pull-up resistance 30 50 110 kohm v il input low-level voltage v vdd = 3.0v -0.3 0.3*v vdd v v vdd = 1.62v -0.3 0.3*v vdd
48 32145bs?01/2012 at32uc3l0128/256 notes: 1. v vdd corresponds to either v vddin or v vddio , depending on the supply for the pin. refer to section 3.2.1 on page 8 for details. 2. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. v ih input high-level voltage v vdd = 3.6v 0.7*v vdd 5.5 v v vdd = 1.98v 0.7*v vdd 5.5 v ol output low-level voltage v vdd = 3.0v, i ol = 6ma 0.4 v v vdd = 1.62v, i ol = 4ma 0.4 v oh output high-level voltage v vdd = 3.0v, i oh = 6ma v vdd -0.4 v v vdd = 1.62v, i oh = 4ma v vdd -0.4 f max output frequency (2) v vdd = 3.0v, load = 10pf 87 mhz v vdd = 3.0v, load = 30pf 58 t rise rise time (2) v vdd = 3.0v, load = 10pf 2.3 ns v vdd = 3.0v, load = 30pf 4.3 t fall fall time (2) v vdd = 3.0v, load = 10pf 1.9 v vdd = 3.0v, load = 30pf 3.7 i leak input leakage current 5.5v, pull-up resistors disabled 10 a c in input capacitance tqfp48 package 4.5 pf qfn48 package 4.2 tllga48 package 4.2 table 7-8. high-drive i/o, 5v toler ant, pin characteristics (1) symbol parameter condition min typ max units table 7-9. twi pin characteristics (1) symbol parameter condition min typ max units r pullup pull-up resistance 25 35 60 kohm v il input low-level voltage v vdd = 3.0v -0.3 0.3*v vdd v v vdd = 1.62v -0.3 0.3*v vdd v ih input high-level voltage v vdd = 3.6v 0.7*v vdd v vdd + 0.3 v v vdd = 1.98v 0.7*v vdd v vdd + 0.3 input high-level voltage, 5v tolerant smbus compliant pins v vdd = 3.6v 0.7*v vdd 5.5 v v vdd = 1.98v 0.7*v vdd 5.5 v ol output low-level voltage i ol = 3ma 0.4 v i leak input leakage current pull-up resistors disabled 1 a i il input low leakage 1 i ih input high leakage 1 c in input capacitance tqfp48 package 3.8 pf qfn48 package 3.5 tllga48 package 3.5
49 32145bs?01/2012 at32uc3l0128/256 note: 1. v vdd corresponds to either v vddin or v vddio , depending on the supply for the pin. refer to section 3.2.1 on page 8 for details. 7.6 oscillator characteristics 7.6.1 oscillator 0 (osc0) characteristics 7.6.1.1 digital clock characteristics the following table describes the characteristics for the oscillator when a digital clock is applied on xin. note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 7.6.1.2 crystal oscilla tor characteristics the following table describes the characteristics for the oscillator when a crystal is connected between xin and xout as shown in figure 7-3 . the user must choose a crystal oscillator where the crystal load capacitance c l is within the range given in the table. the exact value of c l can be found in the crystal datasheet. the capacitance of the external capacitors (c lext ) can then be computed as follows: where c pcb is the capacitance of the pcb and c i is the internal equivalent load capacitance. t fall fall time cbus = 400pf, v vdd > 2.0v 250 ns cbus = 400pf, v vdd > 1.62v 470 f max max frequency cbus = 400pf, v vdd > 2.0v 400 khz table 7-9. twi pin characteristics (1) symbol parameter condition min typ max units table 7-10. digital clock ch aracteristics symbol parameter conditions min typ max units f cpxin xin clock frequency 50 mhz t cpxin xin clock duty cycle (1) 40 60 % t startup startup time 0 cycles c in xin input capacitance tqfp48 package 7.0 pf qfn48 package 6.7 tllga48 package 6.7 c lext 2c l c i ? () c pcb ? =
50 32145bs?01/2012 at32uc3l0128/256 notes: 1. please refer to th e scif chapter for details. 2. nominal crystal cycles. 3. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. figure 7-3. oscillator connection 7.6.2 32khz crystal oscillator (osc32k) characteristics figure 7-3 and the equation above also applies to the 32khz oscillator connection. the user must choose a crystal oscillator wh ere the crystal load capacitance c l is within the range given in the table. the exact value of c l can then be found in the crystal datasheet. table 7-11. crystal oscillator characteristics symbol parameter conditions min typ max unit f out crystal oscillator frequency (3) 0.45 10 16 mhz c l crystal load capacitance (3) 618 pf c i internal equivalent load capacitance 2 t startup startup time scif.oscctrl.gain = 2 (1) 30 000 (2) cycles i osc current consumption active mode, f = 0.45mhz, scif.oscctrl.gain = 0 30 a active mode, f = 10mhz, scif.oscctrl.gain = 2 220 xin xout c lext c lext c l c i uc3l
51 32145bs?01/2012 at32uc3l0128/256 notes: 1. nominal crystal cycles. 2. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 7.6.3 phase locked loop (pll) characteristics note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. table 7-12. 32 khz crystal oscillator characteristics symbol parameter conditions min typ max unit f out crystal oscillator frequency 32 768 hz t startup startup time r s = 60kohm, c l = 9pf 30 000 (1) cycles c l crystal load capacitance (2) 612.5 pf c i internal equivalent load capacitance 2 i osc32 current consumption 0.6 a r s equivalent series resistance (2) 32 768hz 35 85 kohm table 7-13. phase locked loop characteristics symbol parameter conditions min typ max unit f out output frequency (1) 40 240 mhz f in input frequency (1) 416 i pll current consumption 8 a/mhz t startup startup time, from enabling the pll until the pll is locked f in = 4mhz 200 s f in = 16mhz 155
52 32145bs?01/2012 at32uc3l0128/256 7.6.4 digital frequency locked loop (dfll) characteristics notes: 1. spread spectrum generator (ssg) is disabled by wr iting a zero to the en bit in the dfll0ssg register. 2. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 3. the fine and coarse values are selected by wrirting to the dfll0val.fine and dfll0val.coarse field respectively. table 7-14. digital frequency locked loop characteristics symbol parameter conditions min typ max unit f out output frequency (2) 20 150 mhz f ref reference frequency (2) 8 150 khz fine resolution step fine > 100, all coarse values (3) 0.38 % frequency drift over voltage and temperature open loop mode see figure 7-4 accuracy (2) fine lock, f ref = 32khz, ssg disabled 0.1 0.5 % accurate lock, f ref = 32khz, dither clk rcsys/2, ssg disabled 0.06 0.5 fine lock, f ref = 8-150khz, ssg disabled 0.2 1 accurate lock, f ref = 8-150khz, dither clk rcsys/ 2, ssg disabled 0.1 1 i dfll power consumption 25 a/mhz t startup startup time (2) within 90% of final values 100 s t lock lock time f ref = 32khz, fine lock, ssg disabled 8 ms f ref = 32khz, accurate lock, dithering clock = rcsys/2, ssg disabled 28
53 32145bs?01/2012 at32uc3l0128/256 figure 7-4. dfll open loop frequency variation (1)(2) notes: 1. the plot shows a typical open loop mode behavior with coarse= 99 and fine= 255 2. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 7.6.5 120mhz rc oscillator (rc120m) characteristics note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. table 7-15. internal 120mhz rc oscillator characteristics symbol parameter conditions min typ max unit f out output frequency (1) 88 120 152 mhz i rc120m current consumption 1.2 ma t startup startup time (1) v vddcore = 1.8v 3 s dfll open loop frequency variation 80 90 100 110 120 130 140 150 160 -40-20 0 204060 80 temperature frequencies (mhz) 1,98v 1,8v 1.62v
54 32145bs?01/2012 at32uc3l0128/256 7.6.6 32khz rc oscillator (rc32k) characteristics note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 7.6.7 system rc oscillator (rcsys) characteristics 7.7 flash characteristics table 7-18 gives the device maximum operating frequency depending on the number of flash wait states and the flash read mode. the fsw bit in the flashcdw fsr register controls the number of wait states used wh en accessing the flash memory. table 7-16. 32khz rc oscillator characteristics symbol parameter conditions min typ max unit f out output frequency (1) 20 32 44 khz i rc32k current consumption 0.7 a t startup startup time (1) 100 s table 7-17. system rc oscillator characteristics symbol parameter conditions min typ max unit f out output frequency calibrated at 85 c 111.6 115 118.4 khz table 7-18. maximum operating frequency flash wait states read mode maximum operating frequency 1 high speed read mode 50mhz 0 25mhz 1 normal read mode 30mhz 0 15mhz table 7-19. flash characteristics symbol parameter conditions min typ max unit t fpp page programming time f clk_hsb = 50mhz 5 ms t fpe page erase time 5 t ffp fuse programming time 1 t fea full chip erase time (ea) 6 t fce jtag chip erase time (chip_erase) f clk_hsb = 115khz 310
55 32145bs?01/2012 at32uc3l0128/256 7.8 analog characteristics 7.8.1 voltage regulator characteristics note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. note: 1. refer to section 6.1.2 on page 36 . table 7-20. flash endurance and data retention symbol parameter condit ions min typ max unit n farray array endurance (write/page) 100k cycles n ffuse general purpose fuses endurance (write/bit) 10k t ret data retention 15 years table 7-21. vreg electrical characteristics symbol parameter condition min typ max units v vddin input voltage range 1.98 3.3 3.6 v v vddcore output voltage, calibrated value v vddin >= 1.98v 1.8 output voltage accuracy (1) i out = 0.1ma to 60ma, v vddin > 1.98v 2 % i out = 0.1ma to 60ma, v vddin < 1.98v 4 i out dc output current (1) normal mode 60 ma low power mode 1 i vreg static current of internal regulator normal mode 13 a low power mode 4 table 7-22. decoupling requirements symbol parameter condition typ techno. units c in1 input regulator capacitor 1 33 nf c in2 input regulator capacitor 2 100 c in3 input regulator capacitor 3 10 f c out1 output regulator capacitor 1 100 nf c out2 output regulator capacitor 2 2.2 tantalum 0.5 56 32145bs?01/2012 at32uc3l0128/256 7.8.2 power-on reset 18 characteristics note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. figure 7-5. por18 operating principle table 7-23. por18 characteristics symbol parameter condition min typ max units v pot+ voltage threshold on v vddcore rising 1.45 1.58 v v pot- voltage threshold on v vddcore falling 1.2 1.32 t det detection time (1) time with vddcore < v pot- necessary to generate a reset signal 460 s i por18 current consumption 4 a t startup startup time (1) 6s reset v vddcore v pot+ v pot- time
57 32145bs?01/2012 at32uc3l0128/256 7.8.3 power-on reset 33 characteristics note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. figure 7-6. por33 operating principle table 7-24. por33 characteristics symbol parameter condition min typ max units v pot+ voltage threshold on v vddin rising 1.49 1.58 v v pot- voltage threshold on v vddin falling 1.3 1.45 t det detection time (1) time with vddin < v pot- necessary to generate a reset signal 460 s i por33 current consumption 20 a t startup startup time (1) 400 s reset v vddin v pot+ v pot- time
58 32145bs?01/2012 at32uc3l0128/256 7.8.4 brown out detector characteristics the values in table 7-25 describe the values of the bodlevel in the flash general purpose fuse register. 7.8.5 supply monitor 33 characteristics notes: 1. calibration value can be read from the sm33.calib field. this field is updated by the flash fuses after a reset. refer to scif chapter for details. 2. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. table 7-25. bodlevel values bodlevel value min typ max units 011111 binary (31) 0x1f 1.60 v 100111 binary (39) 0x27 1.69 table 7-26. bod characteristics symbol parameter condition min typ max units v hyst bod hysteresis t = 25 c10mv t det detection time time with vddcore < bodlevel necessary to generate a reset signal 1s i bod current consumption 7 a t startup startup time 5s table 7-27. sm33 characteristics symbol parameter condition min typ max units v th voltage threshold calibrated (1) , t = 25 c 1.675 1.75 1.825 v step size, between adjacent values in scif.sm33.calib (2) 11 mv v hyst hysteresis (2) 30 t det detection time time with vddin < v th necessary to generate a reset signal 280 s i sm33 current consumption normal mode 17 a t startup startup time normal mode 140 s
59 32145bs?01/2012 at32uc3l0128/256 7.8.6 analog to digital converter characteristics note: these values are based on simulation and characterization of other avr microcontrollers ma nufactured in the same process technology. these values are not covered by test limits in production. 7.8.6.1 inputs and sample and hold acquisition times note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. the analog voltage source must be able to charge the sample and hold (s/h) capacitor in the adc in order to achieve maximum accuracy. seen externally the adc input consists of a resis- tor ( ) and a capacitor ( ). in addition, the resistance ( ) and capacitance ( ) of the pcb and source must be taken into account when calculating the required sample and hold time. figure 7-7 shows the adc input channel equivalent circuit. table 7-28. adc characteristics symbol parameter conditions min typ max units f adc adc clock frequency 12-bit resolution mode 6 mhz f adc adc clock frequency 10-bit resolution mode 6 mhz 8-bit resolution mode 6 t startup startup time return from idle mode 15 s t conv conversion time (latency) f adc = 6mhz 11 26 cycles throughput rate v vdd > 3.0v, f adc = 6mhz, 12-bit resolution mode, low impedance source 28 ksps throughput rate v vdd > 3.0v, f adc = 6mhz, 10-bit resolution mode, low impedance source 460 ksps v vdd > 3.0v, f adc = 6mhz, 8-bit resolution mode, low impedance source 460 v advrefp reference voltage range v advrefp = v vddana 1.62 1.98 v i adc current consumption on v vddana adc clock = 6mhz 350 a i advrefp current consumption on advrefp pin f adc = 6mhz 150 table 7-29. analog inputs symbol parameter conditions min typ max units v adn input voltage range 12-bit mode 0v advrefp v 10-bit mode 8-bit mode c onchip internal capacitance (1) 22.5 pf r onchip internal resistance (1) v vddio = 3.0v to 3.6v, v vddcore = 1.8v 3.15 kohm v vddio = v vddcore = 1.62v to 1.98v 55.9 r onchip c onchip r source c source
60 32145bs?01/2012 at32uc3l0128/256 figure 7-7. adc input the minimum sample and hold time (in ns) can be found using this formula: where n is the number of bits in the conversion. is defined by the shtim field in the adcifb acr register. please refer to the adcifb chapter for more information. 7.8.6.2 applicable condit ions and derating data note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. adcvrefp/2 c onchip r onchip positive input r source c source v in t samplehold r onchip r source + () c onchip c source + () 2 n 1 + () ln t samplehold table 7-30. transfer characteristics 12-bit resolution mode (1) parameter conditions min typ max units resolution 12 bit integral non-linearity adc clock frequency = 6mhz, input voltage range = 0 - v advrefp +/-4 lsb adc clock frequency = 6mhz, input voltage range = (10% v advrefp ) - (90% v advrefp ) +/-2 differential non-linearity adc clock frequency = 6mhz -1.5 1.5 offset error +/-3 gain error +/-5 table 7-31. transfer characteristics, 10-bit resolution mode (1) parameter conditions min typ max units resolution 10 bit integral non-linearity adc clock frequency = 6mhz +/-1 lsb differential non-linearity -1 1 offset error +/-1 gain error +/-2
61 32145bs?01/2012 at32uc3l0128/256 note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 7.8.7 temperature sensor characteristics note: 1. the temperature sensor is not calib rated. the accuracy of the temperature s ensor is governed by the adc accuracy. table 7-32. transfer characteristics, 8-bit resolution mode (1) parameter conditions min typ max units resolution 8bit integral non-linearity adc clock frequency = 6mhz +/-0.5 lsb differential non-linearity -0.3 0.3 offset error +/-1 gain error +/-1 table 7-33. temperature sensor characteristics (1) symbol parameter condition min typ max units gradient 1mv/ c i ts current consumption 1 a t startup startup time 0s
62 32145bs?01/2012 at32uc3l0128/256 7.8.8 analog comparator characteristics notes: 1. ac.confn.flen and ac.confn.hys fields, refe r to the analog comparator interface chapter. 2. referring to f ac . 3. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 7.8.9 capacitive touch characteristics 7.8.9.1 discharge current source note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. table 7-34. analog comparator characteristics symbol parameter condition min typ max units positive input voltage range (3) -0.2 v vddio + 0.3 v negative input voltage range (3) -0.2 v vddio - 0.6 statistical offset (3) v acrefn = 1.0v, f ac = 12mhz, filter length = 2, hysteresis = 0 (1) 20 mv f ac clock frequency for gclk4 (3) 12 mhz throughput rate (3) f ac = 12mhz 12 000 000 comparisons per second propagation delay delay from input change to interrupt status register changes ns i ac current consumption (3) all channels, vddio = 3.3v, f a = 3mhz 420 a t startup startup time 3 cycles input current per pin (3) 0.2 a/mhz (2) table 7-35. dics characteristics symbol parameter min typ max unit r ref internal resistor 170 kohm k trim step size (1) 0.7 % 1 t clkacifb f ac ---------------------------------------- 3 + ?? ?? t clkacifb
63 32145bs?01/2012 at32uc3l0128/256 7.8.9.2 strong pull-up pull-down table 7-36. strong pull-up pull-down parameter min typ max unit pull-down resistor 1 kohm pull-up resistor 1
64 32145bs?01/2012 at32uc3l0128/256 7.9 timing characteristics 7.9.1 startup, reset, and wake-up timing the startup, reset, and wake-up timings are calculated using the following formula: where and are found in table 7-37 . is the period of the cpu clock. if a clock source other than rcsys is selected as the cpu clock, the oscillator startup time, , must be added to the wake-up time from the stop, deepstop, and static sleep modes. please refer to the source for the cpu clock in the ?oscillator characteristics? on page 49 for more details about oscillator startup times. note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 7.9.2 reset_n timing note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. tt const n cpu t cpu + = t const n cpu t cpu t oscstart table 7-37. maximum reset and wake-up timing (1) parameter measuring max (in s) max startup time from power-up, using regulator time from vddin crossing the v pot+ threshold of por33 to the first instruction entering the decode stage of cpu. vddcore is supplied by the internal regulator. 2210 0 startup time from power-up, no regulator time from vddin crossing the v pot+ threshold of por33 to the first instruction entering the decode stage of cpu. vddcore is connected to vddin. 1810 0 startup time from reset release time from releasing a reset source (except por18, por33, and sm33) to the first instruction entering the decode stage of cpu. 170 0 wake-up idle from wake-up event to the first instruction of an interrupt routine entering the decode stage of the cpu. 019 frozen 0110 standby 0110 stop 27 + 116 deepstop 27 + 116 static 97 + 116 wake-up from shutdown from wake-up event to the first instruction entering the decode stage of the cpu. 1180 0 t const n cpu t oscstart t oscstart t oscstart table 7-38. reset_n waveform parameters (1) symbol parameter conditions min max units t reset reset_n minimum pulse length 10 ns
65 32145bs?01/2012 at32uc3l0128/256 7.9.3 usart in spi mode timing 7.9.3.1 master mode figure 7-8. usart in spi master mode with (cpo l= cpha= 0) or (cpol= cpha= 1) figure 7-9. usart in spi master mode with (cpol= 0 and cpha= 1) or (cpol= 1 and cpha= 0) notes: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 2. where: uspi0 uspi1 miso spck mosi uspi2 uspi3 uspi4 miso spck mosi uspi5 table 7-39. usart in spi mode timing, master mode (1) symbol parameter conditions min max units uspi0 miso setup time before spck rises v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 28.7 + t sample (2) ns uspi1 miso hold time after spck rises 0 uspi2 spck rising to mosi delay 16.5 uspi3 miso setup time be fore spck falls 25.8 + t sample (2) uspi4 miso hold time after spck falls 0 uspi5 spck falling to mosi delay 21.19 t sample t spck t spck 2 t clkusart ------------------------------------ 1 2 -- - ?? ?? t clkusart ? =
66 32145bs?01/2012 at32uc3l0128/256 maximum spi frequency, master output the maximum spi master output frequenc y is given by the following formula: where is the mosi delay, uspi2 or uspi5 depending on cpol and ncpha. is the maximum frequency of the spi pins. please refe r to the i/o pin characteristics section for the maximum frequency of the pins. is the maximum frequency of the clk_spi. refer to the spi chapter for a description of this clock. maximum spi frequency, master input the maximum spi master input frequenc y is given by the following formula: where is the miso setup and hold time, uspi0 + uspi1 or uspi3 + uspi4 depending on cpol and ncpha. is the spi slave response time. please refer to the spi slave datasheet for . is the maximum frequency of the clk_spi. refer to the spi chap- ter for a description of this clock. 7.9.3.2 slave mode figure 7-10. usart in spi slave mode with (cpol= 0 and cpha= 1) or (cpol= 1 and cpha= 0) f spckmax min f pinmax 1 spin ------------ f clkspi 2 9 ---------------------------- - , (, ) = spin f pinmax f clkspi f spckmax min 1 spin t valid + ----------------------------------- - f clkspi 2 9 ---------------------------- - (,) = spin t valid t valid f clkspi uspi7 uspi8 miso spck mosi uspi6
67 32145bs?01/2012 at32uc3l0128/256 figure 7-11. usart in spi slave mode with (cpol= cpha= 0) or (cpol= cpha= 1) figure 7-12. usart in spi slave mode, npcs timing notes: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. 2. where: uspi10 uspi11 miso spck mosi uspi9 uspi14 uspi12 uspi15 uspi13 nss spck, cpol=0 spck, cpol=1 table 7-40. usart in spi mode timing, slave mode (1) symbol parameter conditions min max units uspi6 spck falling to miso delay v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 37.3 ns uspi7 mosi setup time before spck rises 2.6 + t sample (2) + t clk_usart uspi8 mosi hold time after spck rises 0 uspi9 spck rising to miso delay 37.0 uspi10 mosi setup time before spck falls 2.6 + t sample (2) + t clk_usart uspi11 mosi hold time after spck falls 0 uspi12 nss setup time before spck rises 27.2 uspi13 nss hold time after spck falls 0 uspi14 nss setup time before spck falls 27.2 uspi15 nss hold time after spck rises 0 t sample t spck t spck 2 t clkusart ------------------------------------ 1 2 -- - + ?? ?? t clkusart ? =
68 32145bs?01/2012 at32uc3l0128/256 maximum spi frequency, slave input mode the maximum spi slave input frequency is given by the following formula: where is the mosi setup and hold time, uspi7 + uspi8 or uspi10 + uspi11 depending on cpol and ncpha. is the maximum frequency of the clk_spi. refer to the spi chapter for a description of this clock. maximum spi frequency, slave output mode the maximum spi slave output frequency is given by the following formula: where is the miso delay, uspi6 or uspi9 depending on cpol and ncpha. is the spi master setup time. please refer to the spi master datasheet for . is the maximum frequency of the clk_spi. refer to the spi chapter for a description of this clock. is the maximum frequency of the spi pins. please refer to the i/o pin characteris- tics section for the maximum frequency of the pins. 7.9.4 spi timing 7.9.4.1 master mode figure 7-13. spi master mode with (cpol= nc pha= 0) or (cpol= ncpha= 1) f spckmax min f clkspi 2 9 ---------------------------- - 1 spin ------------ (,) = spin f clkspi f spckmax min f clkspi 2 9 ---------------------------- - f pinmax , 1 spin t setup + ------------------------------------ (,) = spin t setup t setup f clkspi f pinmax spi0 spi1 miso spck mosi spi2
69 32145bs?01/2012 at32uc3l0128/256 figure 7-14. spi master mode with (cpol= 0 and ncpha= 1) or (cpol= 1 and ncpha= 0) note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. maximum spi frequency, master output the maximum spi master output frequenc y is given by the following formula: where is the mosi delay, spi2 or spi5 depending on cpol and ncpha. is the maximum frequency of the spi pins. please refer to the i/o pin characteristics section for the maximum frequency of the pins. maximum spi frequency, master input the maximum spi master input frequenc y is given by the following formula: where is the miso setup and hold time, spi0 + spi1 or spi3 + spi4 depending on cpol and ncpha. is the spi slave response time. please refer to the spi slave datasheet for . spi3 spi4 miso spck mosi spi5 table 7-41. spi timing, master mode (1) symbol parameter conditions min max units spi0 miso setup time before spck rises v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 33.4 + (t clk_spi )/2 ns spi1 miso hold time after spck rises 0 spi2 spck rising to mosi delay 7.1 spi3 miso setup time befo re spck falls 29.2 + (t clk_spi )/2 spi4 miso hold time after spck falls 0 spi5 spck falling to mosi delay 8.63 f spckmax min f pinmax 1 spin ------------ (,) = spin f pinmax f spckmax 1 spin t valid + ----------------------------------- - = spin t valid t valid
70 32145bs?01/2012 at32uc3l0128/256 7.9.4.2 slave mode figure 7-15. spi slave mode with (cpol= 0 and ncpha= 1) or (cpol= 1 and ncpha= 0) figure 7-16. spi slave mode with (cpol= ncp ha= 0) or (cpol= ncpha= 1) figure 7-17. spi slave mode, npcs timing spi7 spi8 miso spck mosi spi6 spi10 spi11 miso spck mosi spi9 spi14 spi12 spi15 spi13 npcs spck, cpol=0 spck, cpol=1
71 32145bs?01/2012 at32uc3l0128/256 note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. maximum spi frequency, slave input mode the maximum spi slave input frequency is given by the following formula: where is the mosi setup and hold time, spi7 + spi8 or spi10 + spi11 depending on cpol and ncpha. is the maximum frequency of the clk_spi. refer to the spi chap- ter for a description of this clock. maximum spi frequency, slave output mode the maximum spi slave output frequency is given by the following formula: where is the miso delay, spi6 or spi9 depending on cpol and ncpha. is the spi master setup time. please refer to the spi master datasheet for . is the max- imum frequency of the spi pins. please refer to the i/o pin characteristics section for the maximum frequency of the pins. 7.9.5 twim/twis timing figure 7-43 shows the twi-bus timing requirements and the compliance of the device with them. some of these requirements (t r and t f ) are met by the device without requiring user inter- vention. compliance with the other requirements (t hd-sta , t su-sta , t su-sto , t hd-dat , t su-dat-twi , t low- twi , t high , and f twck ) requires user intervention through appropriate programming of the relevant table 7-42. spi timing, slave mode (1) symbol parameter conditions min max units spi6 spck falling to miso delay v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 29.4 ns spi7 mosi setup time before spck rises 0 spi8 mosi hold time after spck rises 6.0 spi9 spck rising to miso delay 29.0 spi10 mosi setup time before spck falls 0 spi11 mosi hold time after spck falls 5.5 spi12 npcs setup time before spck rises 3.4 spi13 npcs hold time after spck falls 1.1 spi14 npcs setup time before spck falls 3.3 spi15 npcs hold time after spck rises 0.7 f spckmax min f clkspi 1 spin ------------ (,) = spin f clkspi f spckmax min f pinmax 1 spin t setup + ------------------------------------ (, ) = spin t setup t setup f pinmax
72 32145bs?01/2012 at32uc3l0128/256 twim and twis user interface registers. please refer to the twim and twis sections for more information. notes: 1. standard mode: ; fast mode: . 2. a device must internally provide a hold time of at least 300 ns for twd with reference to the falling edge of twck. notations: c b = total capacitance of one bus line in pf t clkpb = period of twi peripheral bus clock t prescaled = period of twi internal prescaled clock (see chapters on twim and twis) the maximum t hd;dat has only to be met if the device does not stretch the low period (t low-twi ) of twck. table 7-43. twi-bus timing requirements symbol parameter mode minimum maximum unit requirement device requirement device t r twck and twd rise time standard (1) - 1000 ns fast (1) 20 + 0.1c b 300 t f twck and twd fall time standard - 300 ns fast 20 + 0.1c b 300 t hd-sta (repeated) start hold time standard 4 t clkpb - s fast 0.6 t su-sta (repeated) start set-up time standard 4.7 t clkpb - s fast 0.6 t su-sto stop set-up time standard 4.0 4t clkpb - s fast 0.6 t hd-dat data hold time standard 0.3 (2) 2t clkpb 3.45 () 15t prescaled + t clkpb s fast 0.9 () t su-dat-twi data set-up time standard 250 2t clkpb -ns fast 100 t su-dat --t clkpb -- t low-twi twck low period standard 4.7 4t clkpb - s fast 1.3 t low --t clkpb -- t high twck high period standard 4.0 8t clkpb - s fast 0.6 f twck twck frequency standard - 100 khz fast 400 1 12t clkpb ----------------------- - f twck 100 khz f twck 100 khz >
73 32145bs?01/2012 at32uc3l0128/256 7.9.6 jtag timing figure 7-18. jtag interface signals note: 1. these values are based on simulation and characterization of other avr microcontrollers manufactured in the same pro- cess technology. these values are not covered by test limits in production. jtag2 jtag3 jtag1 jtag4 jtag0 tms/tdi tck tdo jtag5 jtag6 jtag7 jtag8 jtag9 jtag10 boundary scan inputs boundary scan outputs table 7-44. jtag timings (1) symbol parameter conditions min max units jtag0 tck low half-period v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 21.8 ns jtag1 tck high half-period 8.6 jtag2 tck period 30.3 jtag3 tdi, tms setup before tck high 2.0 jtag4 tdi, tms hold after tck high 2.3 jtag5 tdo hold time 9.5 jtag6 tck low to tdo valid 21.8 jtag7 boundary scan inputs setup time 0.6 jtag8 boundary scan inputs hold time 6.9 jtag9 boundary scan outputs hold time 9.3 jtag10 tck to boundary scan outputs valid 32.2
74 32145bs?01/2012 at32uc3l0128/256 8. mechanical characteristics 8.1 thermal considerations 8.1.1 thermal data table 8-1 summarizes the thermal resistance data depending on the package. 8.1.2 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following: 1. 2. where: ? ja = package thermal resistance, junction-to-ambient (c/w), provided in table 8-1 . ? jc = package thermal resistance, junction-to-ca se thermal resistance (c/w), provided in table 8-1 . ? heat sink = cooling device thermal resistance (c/w), provided in the device datasheet. ?p d = device power consumption (w) estimated from data provided in section 7.4 on page 42 . ?t a = ambient temperature (c). from the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. if a coolin g device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature t j in c. table 8-1. thermal resistance data symbol parameter condition package typ unit ja junction-to-ambient thermal resistance still air tqfp48 54.4 c/w jc junction-to-case thermal resistance tqfp48 15.7 ja junction-to-ambient thermal resistance still air qfn48 26.0 c/w jc junction-to-case thermal resistance qfn48 1.6 ja junction-to-ambient thermal resistance still air tllga48 25.4 c/w jc junction-to-case thermal resistance tllga48 12.7 t j t a p d ja () + = t j t a p ( d ( heatsink jc )) ++ =
75 32145bs?01/2012 at32uc3l0128/256 8.2 package drawings figure 8-1. tqfp-48 package drawing table 8-2. device and package maximum weight 140 mg table 8-3. package characteristics moisture sensitivity level msl3 table 8-4. package reference jedec drawing reference ms-026 jesd97 classification e3
76 32145bs?01/2012 at32uc3l0128/256 figure 8-2. qfn-48 package drawing note: the exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliabil ity. table 8-5. device and package maximum weight 140 mg table 8-6. package characteristics moisture sensitivity level msl3 table 8-7. package reference jedec drawing reference m0-220 jesd97 classification e3
77 32145bs?01/2012 at32uc3l0128/256 figure 8-3. tllga-48 package drawing table 8-8. device and package maximum weight 39.3 mg table 8-9. package characteristics moisture sensitivity level msl3 table 8-10. package reference jedec drawing reference n/a jesd97 classification e4
78 32145bs?01/2012 at32uc3l0128/256 8.3 soldering profile table 8-11 gives the recommended soldering profile from j-std-20. a maximum of three reflow passes is allowed per component. table 8-11. soldering profile profile feature green package average ramp-up rate (217c to peak) 3c/s max preheat temperature 175c 25c 150-200c time maintained above 217c 60-150 s time within 5 c of actual peak temperature 30 s peak temperature range 260c ramp-down rate 6c/s max time 25 c to peak temperature 8 minutes max
79 32145bs?01/2012 at32uc3l0128/256 9. ordering information table 9-1. ordering information device ordering code carrier type package package type temperature operating range at32uc3l0256 at32uc3l0256-autes es tqfp 48 jesd97 classification e3 industrial (-40 c to 85 c) at32uc3l0256-aut tray at32uc3l0256-aur tape & reel AT32UC3L0256-ZAUTES es qfn 48 at32uc3l0256-zaut tray at32uc3l0256-zaur tape & reel at32uc3l0256-d3hes es tllga 48 jesd97 classification e4 at32uc3l0256-d3ht tray at32uc3l0256-d3hr tape & reel at32uc3l0128 at32uc3l0128-aut tray tqfp 48 jesd97 classification e3 at32uc3l0128-aur tape & reel at32uc3l0128-zaut tray qfn 48 at32uc3l0128-zaur tape & reel at32uc3l0128-d3ht tray tllga 48 jesd97 classification e4 at32uc3l0128-d3hr tape & reel
80 32145bs?01/2012 at32uc3l0128/256 10. errata 10.1 rev. c 10.1.1 scif 1. the rc32k output on pa20 is not always permanently disabled the rc32k output on pa20 may sometimes re-appear. fix/workaround before using rc32k for other purposes, the following procedure has to be followed in order to properly disable it: - run the cpu on rcsys - disable the output to pa20 by writing a zero to pm.ppcr.rc32out - enable rc32k by writing a one to scif.rc 32kcr.en, and wait for this bit to be read as one - disable rc32k by writing a ze ro to scif.rc32kcr.en, and wait for this bit to be read as zero. 2. pllcount value larger than zero can cause pllen glitch initializing the pllcount with a value greater than zero creates a glitch on the pllen sig- nal during asynchronous wake up. fix/workaround the lock-masking mechanism for the pll should not be used. the pllcount field of the pll control register should always be written to zero. 3. writing 0x5a5a5a5a to the scif memory range will enable the scif unlock feature the scif unlock feature will be enabled if the val ue 0x5a5a5a5a is written to any loca- tion in the scif memory range. fix/workaround none. 10.1.2 spi 1. spi data transfer hangs with csr0.csaat==1 and mr.modfdis==0 when csr0.csaat==1 and mode fault detection is enabled (mr.modfdis==0), the spi module will not start a data transfer. fix/workaround disable mode fault detection by writing a one to mr.modfdis. 2. disabling spi has no effect on the sr.tdre bit disabling spi has no effect on the sr.tdre bit whereas the write data command is filtered when spi is disabled. writing to tdr when spi is disabled will not clear sr.tdre. if spi is disabled during a pdca transfer, the pdca will continue to write data to tdr until its buffer is empty, and this data will be lost. fix/workaround disable the pdca, add two nops, and disable the spi. to continue the transfer, enable the spi and pdca. 3. spi disable does not work in slave mode spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset by writing a one to the software reset bit in the control register (cr.swrst).
81 32145bs?01/2012 at32uc3l0128/256 4. spi bad serial clock generation on 2nd chip_select when scbr=1, cpol=1, and ncpha=0 when multiple chip selects (cs) are in use, if one of the baudrates equal 1 while one (csrn.scbr=1) of the others do not equal 1, and csrn.cpol=1 and csrn.ncpha=0, then an additional pulse will be genera ted on sck. fix/workaround when multiple cs are in use, if one of the baudrates equals 1, the others must also equal 1 if csrn.cpol=1 and csrn.ncpha=0. 5. spi mode fault detection enable causes incorrect behavior when mode fault detection is enabled (mr. modfdis==0), the spi module may not operate properly. fix/workaround always disable mode fault detection before using the spi by writing a one to mr.modfdis. 6. spi rdr.pcs is not correct the pcs (peripheral chip select) field in th e spi rdr (receive data register) does not correctly indicate the value on the npcs pins at the end of a transfer. fix/workaround do not use the pcs field of the spi rdr. 10.1.3 twi 1. smbalert bit may be set after reset the smbus alert (smbalert) bit in the status register (sr) might be erroneously set after system reset. fix/workaround after system reset, clear the sr.smbalert bit before commencing any twi transfer. 2. clearing the nak bit before the btf bit is set locks up the twi bus when the twis is in transmit mode, clearing the nak received (nak) bit of the status reg- ister (sr) before the end of the acknowl edge/not acknowledge cycle will cause the twis to attempt to continue transmitting data, thus locking up the bus. fix/workaround clear sr.nak only after the byte transfer finished (btf) bit of the same register has been set. 10.1.4 tc 1. channel chaining skips first pulse for upper channel when chaining two channels using the block mode register, the first pulse of the clock between the channels is skipped. fix/workaround configure the lower channel with ra = 0x1 and rc = 0x2 to produce a dummy clock cycle for the upper channel. after the dummy cycle has been generated, indicated by the sr.cpcs bit, reconfigure the ra and rc registers for the lower channel with the real values. 10.1.5 cat 1. cat qmatrix sense capacitors discharged prematurely at the end of a qmatrix burst charging sequence that uses different burst count values for different y lines, the y lines may be incorrectly grounded for up to n-1 periods of the periph-
82 32145bs?01/2012 at32uc3l0128/256 eral bus clock, where n is the ratio of t he pb clock frequency to the gclk_cat frequency. this results in premature loss of charge from the sense capacitors and thus increased vari- ability of the acquir ed count values. fix/workaround enable the 1kohm drive resistors on all implemented qmatrix y lines (csa 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the csares register. 2. autonomous cat acquisition must be longer than ast source clock period when using the ast to trigger cat autonomous touch acquisition in sleep modes where the cat bus clock is turned off, the cat will start several acquisitions if the period of the ast source clock is larger than one cat acquisition. one ast clock period after the ast trigger, the cat clock will automatically stop and t he cat acquisition can be stopped prematurely, ruining the result. fix/workaround always ensure that the atcfg1.max field is set so that the duration of the autonomous touch acquisition is greater than one clock period of the ast source clock. 10.1.6 awire 1. awire memory_speed_request comm and does not return correct cv the awire memory_speed_request command does not retu rn a cv co rresponding to the formula in the awire debug interface chapter. fix/workaround issue a dummy read to address 0x100000000 before issuing the memory_speed_request command and use this formula instead: 10.2 rev. b 10.2.1 scif 1. the rc32k output on pa20 is not always permanently disabled the rc32k output on pa20 may sometimes re-appear. fix/workaround before using rc32k for other purposes, the following procedure has to be followed in order to properly disable it: - run the cpu on rcsys - disable the output to pa20 by writing a zero to pm.ppcr.rc32out - enable rc32k by writing a one to scif.rc 32kcr.en, and wait for this bit to be read as one - disable rc32k by writing a ze ro to scif.rc32kcr.en, and wait for this bit to be read as zero. 2. pllcount value larger than zero can cause pllen glitch initializing the pllcount with a value greater than zero creates a glitch on the pllen sig- nal during asynchronous wake up. fix/workaround the lock-masking mechanism for the pll should not be used. the pllcount field of the pll control register should always be written to zero. 3. writing 0x5a5a5a5a to the scif memory range will enable the scif unlock feature f sab 7 f aw cv 3 ? ---------------- - =
83 32145bs?01/2012 at32uc3l0128/256 the scif unlock feature will be enabled if the val ue 0x5a5a5a5a is written to any loca- tion in the scif memory range. fix/workaround none. 10.2.2 wdt 1. wdt control register does not have synchronization feedback when writing to the timeout pr escale select (psel), time ban prescale select (tban), enable (en), or wdt mode (mode) fieldss of the wdt control register (ctrl), a synchro- nizer is started to propagate the values to the wdt clcok domain. this synchronization takes a finite amount of time, but only the status of the synchronization of the en bit is reflected back to the user. writing to the synch ronized fields during synchronization can lead to undefined behavior. fix/workaround -when writing to the affected fields, the user must ensure a wait corresponding to 2 clock cycles of both the wdt peripheral bus clock and the selected wdt clock source. -when doing writes that changes the en bit, the en bit can be read back until it reflects the written value. 10.2.3 spi 1. spi data transfer hangs with csr0.csaat==1 and mr.modfdis==0 when csr0.csaat==1 and mode fault detection is enabled (mr.modfdis==0), the spi module will not start a data transfer. fix/workaround disable mode fault detection by writing a one to mr.modfdis. 2. disabling spi has no effect on the sr.tdre bit disabling spi has no effect on the sr.tdre bit whereas the write data command is filtered when spi is disabled. writing to tdr when spi is disabled will not clear sr.tdre. if spi is disabled during a pdca transfer, the pdca will continue to write data to tdr until its buffer is empty, and this data will be lost. fix/workaround disable the pdca, add two nops, and disable the spi. to continue the transfer, enable the spi and pdca. 3. spi disable does not work in slave mode spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset by writing a one to the software reset bit in the control register (cr.swrst). 4. spi bad serial clock generation on 2nd chip_select when scbr=1, cpol=1, and ncpha=0 when multiple chip selects (cs) are in use, if one of the baudrates equal 1 while one (csrn.scbr=1) of the others do not equal 1, and csrn.cpol=1 and csrn.ncpha=0, then an additional pulse will be genera ted on sck. fix/workaround when multiple cs are in use, if one of the baudrates equals 1, the others must also equal 1 if csrn.cpol=1 and csrn.ncpha=0. 5. spi mode fault detection enable causes incorrect behavior when mode fault detection is enabled (mr. modfdis==0), the spi module may not operate
84 32145bs?01/2012 at32uc3l0128/256 properly. fix/workaround always disable mode fault detection before using the spi by writing a one to mr.modfdis. 6. spi rdr.pcs is not correct the pcs (peripheral chip select) field in th e spi rdr (receive data register) does not correctly indicate the value on the npcs pins at the end of a transfer. fix/workaround do not use the pcs field of the spi rdr. 10.2.4 twi 1. twis may not wake the device from sleep mode if the cpu is put to a sleep mode (except idle and frozen) directly after a twi start condi- tion, the cpu may not wake upon a twis address match. the request is nacked. fix/workaround when using the twi address match to wake t he device from sleep, do not switch to sleep modes deeper than frozen. another solution is to enable asynchronous eic wake on the twis clock (twck) or twis data (twd) pi ns, in order to wake the system up on bus events. 2. smbalert bit may be set after reset the smbus alert (smbalert) bit in the status register (sr) might be erroneously set after system reset. fix/workaround after system reset, clear the sr.smbalert bit before commencing any twi transfer. 3. clearing the nak bit before the btf bit is set locks up the twi bus when the twis is in transmit mode, clearing the nak received (nak) bit of the status reg- ister (sr) before the end of the acknowl edge/not acknowledge cycle will cause the twis to attempt to continue transmitting data, thus locking up the bus. fix/workaround clear sr.nak only after the byte transfer finished (btf) bit of the same register has been set. 10.2.5 pwma 1. the sr.ready bit cannot be cleared by writing to scr.ready the ready bit in the status register will not be cleared when writing a one to the corre- sponding bit in the status clear register. th e ready bit will be cleared when the busy bit is set. fix/workaround disable the ready interrupt in the interrupt handler when receiving the interrupt. when an operation that triggers the busy/ready bit is started, wait until the ready bit is low in the sta- tus register before enabling the interrupt. 10.2.6 tc 1. channel chaining skips first pulse for upper channel when chaining two channels using the block mode register, the first pulse of the clock between the channels is skipped. fix/workaround
85 32145bs?01/2012 at32uc3l0128/256 configure the lower channel with ra = 0x1 and rc = 0x2 to produce a dummy clock cycle for the upper channel. after the dummy cycle has been generated, indicated by the sr.cpcs bit, reconfigure the ra and rc registers for the lower channel with the real values. 10.2.7 cat 1. cat qmatrix sense capacitors discharged prematurely at the end of a qmatrix burst charging sequence that uses different burst count values for different y lines, the y lines may be incorrectly grounded for up to n-1 periods of the periph- eral bus clock, where n is the ratio of t he pb clock frequency to the gclk_cat frequency. this results in premature loss of charge from the sense capacitors and thus increased vari- ability of the acquir ed count values. fix/workaround enable the 1kohm drive resistors on all implemented qmatrix y lines (csa 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the csares register. 2. autonomous cat acquisition must be longer than ast source clock period when using the ast to trigger cat autonomous touch acquisition in sleep modes where the cat bus clock is turned off, the cat will start several acquisitions if the period of the ast source clock is larger than one cat acquisition. one ast clock period after the ast trigger, the cat clock will automatically stop and t he cat acquisition can be stopped prematurely, ruining the result. fix/workaround always ensure that the atcfg1.max field is set so that the duration of the autonomous touch acquisition is greater than one clock period of the ast source clock. 3. cat consumes unnecessary power when disabled or when autonomous touch not used a cat prescaler controlled by the atcfg0.div field will be active even when the cat mod- ule is disabled or when the autonomous touch feature is not used, thereby causing unnecessary power consumption. fix/workaround if the cat module is not used, disable the clk_cat clock in the pm module. if the cat module is used but the autonomous touch feature is not used, the power consumption of the cat module may be reduced by writing 0xffff to the atcfg0.div field. 10.2.8 awire 1. awire memory_speed_request comm and does not return correct cv the awire memory_speed_request command does not retu rn a cv co rresponding to the formula in the awire debug interface chapter. fix/workaround issue a dummy read to address 0x100000000 before issuing the memory_speed_request command and use this formula instead: f sab 7 f aw cv 3 ? ---------------- - =
86 32145bs?01/2012 at32uc3l0128/256 10.3 rev. a 10.3.1 device 1. jtagid is wrong the jtagid is 0x021df03f. fix/workaround none. 10.3.2 flashcdw 1. general-purpose fuse programming does not work the general-purpose fuses cannot be programmed and are stuck at 1. please refer to the fuse settings chapter in the flashcdw for more information about what functions are affected. fix/workaround none. 2. set security bit command does not work the set security bit (ssb) command of the flas hcdw does not work . the device cannot be locked from external jtag, awire, or other debug accesses. fix/workaround none. 3. flash programming time is longer than specified the flash programming time is now : fix/workaround none. 10.3.3 power manager 1. clock failure detector (cfd) can be issued while turning off the cfd while turning off the cfd, the cfd bit in the status register (sr) can be set. this will change the main cl ock source to rcsys. fix/workaround solution 1: enable cfd in terrupt. if cfd interrupt is issues after turning off the cfd, switch back to original main clock source. solution 2: only turn off the cfd while running the main clock on rcsys. 2. sleepwalking in idle and frozen sleep mode will mask all other pb clocks table 10-1. flash characteristics symbol parameter conditions min typ max unit t fpp page programming time f clk_hsb = 50mhz 7.5 ms t fpe page erase time 7.5 t ffp fuse programming time 1 t fea full chip erase time (ea) 9 t fce jtag chip erase time (chip_erase) f clk_hsb = 115khz 250
87 32145bs?01/2012 at32uc3l0128/256 if the cpu is in idle or frozen sleep mode and a module is in a state that triggers sleep walk- ing, all pb clocks will be masked except the pb clock to the sleepwalking module. fix/workaround mask all clock requests in the pm.ppcr register before going into idle or frozen mode. 2. unused pb clocks are running three unused pba clocks are en abled by default and will cause increased active power consumption. fix/workaround disable the clocks by writing zeroes to bits [27: 25] in the pba clock mask register. 10.3.4 scif 1. the rc32k output on pa20 is not always permanently disabled the rc32k output on pa20 may sometimes re-appear. fix/workaround before using rc32k for other purposes, the following procedure has to be followed in order to properly disable it: - run the cpu on rcsys - disable the output to pa20 by writing a zero to pm.ppcr.rc32out - enable rc32k by writing a one to scif.rc 32kcr.en, and wait for this bit to be read as one - disable rc32k by writing a ze ro to scif.rc32kcr.en, and wait for this bit to be read as zero. 2. pll lock might not clear after disable under certain circumstances, the lock signal from the phase locked loop (pll) oscillator may not go back to zero after th e pll oscillator has been disabl ed. this can cause the prop- agation of clock signals with the wrong frequency to parts of the system that use the pll clock. fix/workaround pll must be turned off befor e entering stop, deepstop or static sleep modes. if pll has been turned off, a delay of 30us must be observed after the pll has been enabled again before the scif.pll0lock bit can be used as a valid indication that the pll is locked. 3. pllcount value larger than zero can cause pllen glitch initializing the pllcount with a value greater than zero creates a glitch on the pllen sig- nal during asynchronous wake up. fix/workaround the lock-masking mechanism for the pll should not be used. the pllcount field of the pll control register should always be written to zero. 4. rcsys is not calibrated the rcsys is not calibrated and will run faster than 115.2khz. fre quencies around 150khz can be expected. fix/workaround if a known clock source is available the rc sys can be runtime calibrated by using the fre- quency meter (freqm) and tuning the rcsys by writing to the rccr register in scif. 5. writing 0x5a5a5a5a to the scif memory range will enable the scif unlock feature the scif unlock feature will be enabled if the val ue 0x5a5a5a5a is written to any loca- tion in the scif memory range. fix/workaround
88 32145bs?01/2012 at32uc3l0128/256 none. 10.3.5 wdt 1. clearing the watchdog timer (wdt) counter in second half of timeout period will issue a watchdog reset if the wdt counter is cleared in the second half of the ti meout period, the wdt will immedi- ately issue a watchdog reset. fix/workaround use twice as long timeout period as needed and clear the wdt counter within the first half of the timeout period. if the wdt counter is cl eared after the first half of the timeout period, you will get a watchdog reset immediately. if the wdt counter is not clea red at all, the time before the reset will be tw ice as long as needed. 2. wdt control register does not have synchronization feedback when writing to the timeout pr escale select (psel), time ban prescale select (tban), enable (en), or wdt mode (mode) fieldss of the wdt control register (ctrl), a synchro- nizer is started to propagate the values to the wdt clcok domain. this synchronization takes a finite amount of time, but only the status of the synchronization of the en bit is reflected back to the user. writing to the synch ronized fields during synchronization can lead to undefined behavior. fix/workaround -when writing to the affected fields, the user must ensure a wait corresponding to 2 clock cycles of both the wdt peripheral bus clock and the selected wdt clock source. -when doing writes that changes the en bit, the en bit can be read back until it reflects the written value. 10.3.6 gpio 1. clearing interrupt flags can mask other interrupts when clearing interrupt flags in a gpio port, interrupts on other pins of that port, happening in the same clock cycle will not be registered. fix/workaround read the pvr register of the port before and af ter clearing the interrupt to see if any pin change has happened while clearing the interr upt. if any change occurred in the pvr between the reads, they must be treated as an interrupt. 10.3.7 spi 1. spi data transfer hangs with csr0.csaat==1 and mr.modfdis==0 when csr0.csaat==1 and mode fault detection is enabled (mr.modfdis==0), the spi module will not start a data transfer. fix/workaround disable mode fault detection by writing a one to mr.modfdis. 2. disabling spi has no effect on the sr.tdre bit disabling spi has no effect on the sr.tdre bit whereas the write data command is filtered when spi is disabled. writing to tdr when spi is disabled will not clear sr.tdre. if spi is disabled during a pdca transfer, the pdca will continue to write data to tdr until its buffer is empty, and this data will be lost. fix/workaround disable the pdca, add two nops, and disable the spi. to continue the transfer, enable the spi and pdca.
89 32145bs?01/2012 at32uc3l0128/256 3. spi disable does not work in slave mode spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset by writing a one to the software reset bit in the control register (cr.swrst). 4. spi bad serial clock generation on 2nd chip_select when scbr=1, cpol=1, and ncpha=0 when multiple chip selects (cs) are in use, if one of the baudrates equal 1 while one (csrn.scbr=1) of the others do not equal 1, and csrn.cpol=1 and csrn.ncpha=0, then an additional pulse will be genera ted on sck. fix/workaround when multiple cs are in use, if one of the baudrates equals 1, the others must also equal 1 if csrn.cpol=1 and csrn.ncpha=0. 5. spi mode fault detection enable causes incorrect behavior when mode fault detection is enabled (mr. modfdis==0), the spi module may not operate properly. fix/workaround always disable mode fault detection before using the spi by writing a one to mr.modfdis. 6. spi rdr.pcs is not correct the pcs (peripheral chip select) field in th e spi rdr (receive data register) does not correctly indicate the value on the npcs pins at the end of a transfer. fix/workaround do not use the pcs field of the spi rdr. 10.3.8 twi 1. twis may not wake the device from sleep mode if the cpu is put to a sleep mode (except idle and frozen) directly after a twi start condi- tion, the cpu may not wake upon a twis address match. the request is nacked. fix/workaround when using the twi address match to wake t he device from sleep, do not switch to sleep modes deeper than frozen. another solution is to enable asynchronous eic wake on the twis clock (twck) or twis data (twd) pi ns, in order to wake the system up on bus events. 2. smbalert bit may be set after reset the smbus alert (smbalert) bit in the status register (sr) might be erroneously set after system reset. fix/workaround after system reset, clear the sr.smbalert bit before commencing any twi transfer. 3. clearing the nak bit before the btf bit is set locks up the twi bus when the twis is in transmit mode, clearing the nak received (nak) bit of the status reg- ister (sr) before the end of the acknowl edge/not acknowledge cycle will cause the twis to attempt to continue transmitting data, thus locking up the bus. fix/workaround clear sr.nak only after the byte transfer finished (btf) bit of the same register has been set. 4. twis stretch on address match error
90 32145bs?01/2012 at32uc3l0128/256 when the twis stretches twck due to a slave address match, it also holds twd low for the same duration if it is to be receiving data. when twis releases twck, it releases twd at the same time. this can cause a twi timing violation. fix/workaround none. 5. twim twalm polarity is wrong the twalm signal in the twim is active high instead of active low. fix/workaround use an external inverter to invert the signal going into the twim. when using both twim and twis on the same pins, the twalm cannot be used. 10.3.9 pwma 1. the sr.ready bit cannot be cleared by writing to scr.ready the ready bit in the status register will not be cleared when writing a one to the corre- sponding bit in the status clear register. th e ready bit will be cleared when the busy bit is set. fix/workaround disable the ready interrupt in the interrupt handler when receiving the interrupt. when an operation that triggers the busy/ready bit is started, wait until the ready bit is low in the sta- tus register before enabling the interrupt. 10.3.10 tc 1. channel chaining skips first pulse for upper channel when chaining two channels using the block mode register, the first pulse of the clock between the channels is skipped. fix/workaround configure the lower channel with ra = 0x1 and rc = 0x2 to produce a dummy clock cycle for the upper channel. after the dummy cycle has been generated, indicated by the sr.cpcs bit, reconfigure the ra and rc registers for the lower channel with the real values. 10.3.11 adcifb 1. adcifb dma transfer does not work with divided pba clock dma requests from the adcifb will not be performed when the pba clock is slower than the hsb clock. fix/workaround do not use divided pba clock when th e pdca transfers from the adcifb. 10.3.12 cat 1. cat qmatrix sense capacitors discharged prematurely at the end of a qmatrix burst charging sequence that uses different burst count values for different y lines, the y lines may be incorrectly grounded for up to n-1 periods of the periph- eral bus clock, where n is the ratio of t he pb clock frequency to the gclk_cat frequency. this results in premature loss of charge from the sense capacitors and thus increased vari- ability of the acquir ed count values. fix/workaround enable the 1kohm drive resistors on all implemented qmatrix y lines (csa 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the csares register.
91 32145bs?01/2012 at32uc3l0128/256 2. autonomous cat acquisition must be longer than ast source clock period when using the ast to trigger cat autonomous touch acquisition in sleep modes where the cat bus clock is turned off, the cat will start several acquisitions if the period of the ast source clock is larger than one cat acquisition. one ast clock period after the ast trigger, the cat clock will automatically stop and t he cat acquisition can be stopped prematurely, ruining the result. fix/workaround always ensure that the atcfg1.max field is set so that the duration of the autonomous touch acquisition is greater than one clock period of the ast source clock. 3. cat consumes unnecessary power when disabled or when autonomous touch not used a cat prescaler controlled by the atcfg0.div field will be active even when the cat mod- ule is disabled or when the autonomous touch feature is not used, thereby causing unnecessary power consumption. fix/workaround if the cat module is not used, disable the clk_cat clock in the pm module. if the cat module is used but the autonomous touch feature is not used, the power consumption of the cat module may be reduced by writing 0xffff to the atcfg0.div field. 4. cat module does not terminate qtouch burst on detect the cat module does not terminate a qtouch burst when the detection voltage is reached on the sense capacitor. this can ca use the sense capacitor to be charged more than necessary. depending on the dielectric abso rption characteristics of the capacitor, this can lead to unstable measurements. fix/workaround use the minimum possible value for the max field in the atcfg1, tg0cfg1, and tg1cfg1 registers. 10.3.13 awire 1. awire memory_speed_request comm and does not return correct cv the awire memory_speed_request command does not retu rn a cv co rresponding to the formula in the awire debug interface chapter. fix/workaround issue a dummy read to address 0x100000000 before issuing the memory_speed_request command and use this formula instead: 10.3.14 i/o pins 1. pa05 is not 3.3v tolerant. pa05 should be grounded on the pcb and left unused if vddio is above 1.8v. fix/workaround none. 2. no pull-up on pins that are not bonded pb13 to pb27 are not bonded on uc3l0256/128, but has no pull-up and can cause current consumption on vddio/vddin if left undriven. fix/workaround f sab 7 f aw cv 3 ? ---------------- - =
92 32145bs?01/2012 at32uc3l0128/256 enable pull-ups on pb13 to pb27 by writing 0x0fffe000 to the puers1 register in the gpio. 3. pa17 has low esd tolerance pa17 only tolerates 500v esd pulses (human body model). fix/workaround care must be taken during manufacturing and pcb design.
93 32145bs?01/2012 at32uc3l0128/256 11. datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. 11.1 rev. b ? 01/2012 11.2 rev. a ? 12/2011 1. description: dfll frequency is 20 to 150mhz, not 40 to 150mhz. 2. description: ?one touch sensor can be configured to operate autonomously...? replaced by ?all touch sensors can be configured to operate autonomously...?. 3. block diagram: gclk_in is input, not output, and is 2 bits wide (gclk_in[1..0]). cat smp corrected from i/o to output. spi np cs corrected from output to i/o. 4. package and pinout: prnd signal removed from signal descriptions list table and gpio controller function multiplexing table. 5. supply and startup considerations: in 1.8v si ngle supply mode figure, the input voltage is 1.62-1.98v, not 1.98-3.6v . ?on system start-up, the dfll is disabled? is replaced by ?on system start-up, all high-speed clocks are disabled?. 6. adcifb: prnd signal removed from block diagram. 7. electrical characteristics: added pll source clock in the clock frequencies table in the maximum clock frequencies section. removed 64-pin package information from i/o pin characteristics tables and digital clock characteristics table. 8. electrical characteristics: removed usb transce iver characteristics, as the device contains no usb. 9. mechanical characteristics: added notes to package drawings. 10. summary: removed programming and debugging chapter, added processor and architecture chapter. 11. datasheet revision history: corrected release dat e for datasheet rev. a; the correct date is 12/2011. 1. initial revision.
i 32145bs?01/2012 at32uc3l0128/256 table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 description ............ .............. .............. ............... .............. .............. ............ 3 2 overview ............ ................ ................ ............... .............. .............. ............ 5 2.1 block diagram ...................................................................................................5 2.2 configuration summary .....................................................................................6 3 package and pinout ................. ................ ................. ................ ............... 7 3.1 package .............................................................................................................7 3.2 peripheral multiplexing on i/o lines ..................................................................8 3.3 signal descriptions ..........................................................................................13 3.4 i/o line considerations ...................................................................................16 4 processor and architecture .... ................ ................. ................ ............. 18 4.1 features ..........................................................................................................18 4.2 avr32 architecture .........................................................................................18 4.3 the avr32uc cpu ........................................................................................19 4.4 programming model ........................................................................................23 4.5 exceptions and interrupts ................................................................................27 5 memories ............... .............. .............. ............... .............. .............. .......... 32 5.1 embedded memories ......................................................................................32 5.2 physical memory map .....................................................................................32 5.3 peripheral address map ..................................................................................33 5.4 cpu local bus mapping .................................................................................34 6 supply and startup c onsiderations ............ ................. .............. .......... 36 6.1 supply considerations .....................................................................................36 6.2 startup considerations ....................................................................................40 7 electrical characteristics ... .............. ............... .............. .............. .......... 41 7.1 absolute maximum ratings* ...........................................................................41 7.2 supply characteristics .....................................................................................41 7.3 maximum clock frequencies ..........................................................................42 7.4 power consumption ........................................................................................42 7.5 i/o pin characteristics .....................................................................................46 7.6 oscillator characteristics .................................................................................49 7.7 flash characteristics .......................................................................................54
ii 32145bs?01/2012 at32uc3l0128/256 7.8 analog characteristics .....................................................................................55 7.9 timing characteristics .....................................................................................64 8 mechanical characteristics ....... ................. ................ ................. .......... 74 8.1 thermal considerations ..................................................................................74 8.2 package drawings ...........................................................................................75 8.3 soldering profile ..............................................................................................78 9 ordering information .......... .............. ............... .............. .............. .......... 79 10 errata ............. ................ ................. ................ ................. .............. .......... 80 10.1 rev. c ..............................................................................................................80 10.2 rev. b ..............................................................................................................82 10.3 rev. a ..............................................................................................................86 11 datasheet revision history .. .............. .............. .............. .............. ........ 93 11.1 rev. b ? 01/2012 .............................................................................................93 11.2 rev. a ? 12/2011 .............................................................................................93 table of contents.......... ................. ................ ................. ................ ........... i
32145bs?01/2012 atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel : (+1)(408) 441-0311 fax : (+1)(408) 487-2600 www.atmel.com atmel asia limited unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel : (+852) 2245-6100 fax : (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel : (+49) 89-31970-0 fax : (+49) 89-3194621 atmel japan 16f, shin osaki kangyo bldg. 1-6-4 osaka shinagawa-ku tokyo 104-0032 japan tel : (+81) 3-6417-0300 fax : (+81) 3-6417-0370 ? 2012 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, avr ? , picopower ? , qtouch ? , aks ? and others are registered tr ademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection wi th atmel products. no license, ex press or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its pro ducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purp ose, or non-infringement. in no even t shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitati on, damages for loss and prof- its, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or com- pleteness of the contents of th is document and reserves the right to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information cont ained herein. unless specifically provided otherwise, atmel pr oducts are not suit- able for, and shall not be used in, automotive applications. atme l products are not intended, authorized, or warranted for use as components in applica- tions intended to support or sustain life.

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